From patchwork Thu Mar 21 14:42:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 229719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id DB2EF2C00B6 for ; Fri, 22 Mar 2013 01:42:44 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=OBXo71T523tQa/Z/l0 1MRAedfNtj+c1CnVkvYXkzi8UXXfQFXL2DJ0zYWqvRjCk/wkv83/zfARoE++J+hR imvb9hwcSel5FUKpAfGFTsMDJWQhfGBlSxtpc40vCYFUIRieispyHMml0wewVJq1 I6hIuDXs94igdulugBX2J8T7w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=8Wrb6wssUmnkZRdSQ1MoHjFd YxA=; b=TSrlt5VT6yTEG6L/dlUhaZAcox8PmciPH0wxSdzUWWj14S+Ku/c+pHXC i804IkjI+UI6zmfnrfgftAaCZJfZPBiG/yIzCfrsAXekX3q2enlCrBkEBYzlFU+H cdxCpcrkZWDTQOCXPlGjHJJ3GRBitKMl0Q7W95HoFxR1W0GDec8= Received: (qmail 19176 invoked by alias); 21 Mar 2013 14:42:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18871 invoked by uid 89); 21 Mar 2013 14:42:29 -0000 X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, TW_VB autolearn=ham version=3.3.1 Received: from mail-oa0-f54.google.com (HELO mail-oa0-f54.google.com) (209.85.219.54) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 21 Mar 2013 14:42:24 +0000 Received: by mail-oa0-f54.google.com with SMTP id n12so3177299oag.13 for ; Thu, 21 Mar 2013 07:42:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-received:in-reply-to:references:date:message-id :subject:from:to:cc:content-type:x-gm-message-state; bh=IPXc4DDkIZ0xvr2d4iBLajmvsxaykMZhIwpq7tuu85k=; b=mIyVgYgnMXrP5pQMHCx0twOEqV3FE2LgEH2GsTJQmfpqbCUqcZpToCa/RWPraeVvH8 PxPtme25NPaLVmhFOTsR0IaDOfTGbOc0148uKL57YXbZkKiCa8doRWR13pzX82Mi/hPZ Xm20t4f4nPJ0xQOkbYK8/mVfHF8Wsv520wEQI4WjIn1AExCETg+LQXaOzt8valU6KRru EQvmilpdz6PlaSCHKlrmOuuFFnbIMoNshnvAS5zEF1avdTkFLJZyASS7NsMbEG2lQQ8M v1GPEv9lQ1zvWYj+NKthvtp+djQFRptcRRKsj/o1GkJW1Y7LB45Fe7V/X6ZdxVaHQPEx ru0w== MIME-Version: 1.0 X-Received: by 10.60.10.34 with SMTP id f2mr6783206oeb.104.1363876942785; Thu, 21 Mar 2013 07:42:22 -0700 (PDT) Received: by 10.60.35.202 with HTTP; Thu, 21 Mar 2013 07:42:22 -0700 (PDT) In-Reply-To: <510BFEC7.7000907@arm.com> References: <50CF366B.2060405@arm.com> <510BFEC7.7000907@arm.com> Date: Thu, 21 Mar 2013 15:42:22 +0100 Message-ID: Subject: Re: [ARM] Turning off 64bits ops in Neon and gfortran/modulo-scheduling problem From: Christophe Lyon To: ramrad01@arm.com Cc: Richard Earnshaw , "gcc-patches@gcc.gnu.org" X-Gm-Message-State: ALoCoQniOfzVmQsPrZ6D+8xa+ar2mLVY0EM4ZuRavnA90E6w0b9yE5jSN/qZkTFCp/NCkNPdET7X Here is what I have commited (svn 196876.): a few updates were necessary. Christophe. 2013-03-21 Christophe Lyon gcc/ * config/arm/arm-protos.h (tune_params): Add prefer_neon_for_64bits field. * config/arm/arm.c (prefer_neon_for_64bits): New variable. (arm_slowmul_tune): Default prefer_neon_for_64bits to false. (arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto. (arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto. (arm_cortex_a15_tune, arm_cortex_a5_tune): Ditto. (arm_cortex_a9_tune, arm_v6m_tune, arm_fa726te_tune): Ditto. (arm_option_override): Handle -mneon-for-64bits new option. * config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro. (prefer_neon_for_64bits): Declare new variable. * config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and nota8. (arch_enabled): Handle new arch types. Remove support for onlya8 and nota8. (one_cmpldi2): Use new arch names. (zero_extenddi2, extenddi2): Ditto. * config/arm/arm.opt (mneon-for-64bits): Add option. * config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon) (anddi3_neon, xordi3_neon, ashldi3_neon, di3_neon): Use neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead of onlya8. * doc/invoke.texi (-mneon-for-64bits): Document. gcc/testsuite: * gcc.target/arm/neon-for-64bits-1.c: New tests. * gcc.target/arm/neon-for-64bits-2.c: Likewise. On 1 February 2013 18:43, Ramana Radhakrishnan wrote: > >>> >> Here is a new version of my patch, with the cleanup you requested. >> >> 2012-12-18 Christophe Lyon >> >> gcc/ >> * config/arm/arm-protos.h (tune_params): Add >> prefer_neon_for_64bits field. >> * config/arm/arm.c (prefer_neon_for_64bits): New variable. >> (arm_slowmul_tune): Default prefer_neon_for_64bits to false. >> (arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto. >> (arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto. >> (arm_cortex_a5_tune, arm_cortex_a15_tune): Ditto. >> (arm_cortex_a9_tune, arm_fa726te_tune): Ditto. >> (arm_option_override): Handle -mneon-for-64bits new option. >> * config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro. >> (prefer_neon_for_64bits): Declare new variable. >> * config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to >> avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and >> nota8. >> (arch_enabled): Handle new arch types. Remove support for onlya8 >> and nota8. >> (one_cmpldi2): Use new arch names. >> * config/arm/arm.opt (mneon-for-64bits): Add option. >> * config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon) >> (anddi3_neon, xordi3_neon, ashldi3_neon, di3_neon): Use >> neon_for_64bits instead of nota8 and avoid_neon_for_64bits >> instead >> of onlya8. >> * doc/invoke.texi (-mneon-for-64bits): Document. >> >> gcc/testsuite/ >> * gcc.target/arm/neon-for-64bits-1.c: New tests. >> * gcc.target/arm/neon-for-64bits-2.c: Likewise. >> > > > > Ok for 4.9 stage1 now. > > regards > Ramana > Index: gcc/config/arm/arm-protos.h =================================================================== --- gcc/config/arm/arm-protos.h (revision 196875) +++ gcc/config/arm/arm-protos.h (revision 196876) @@ -269,6 +269,8 @@ struct tune_params bool logical_op_non_short_circuit[2]; /* Vectorizer costs. */ const struct cpu_vec_costs* vec_costs; + /* Prefer Neon for 64-bit bitops. */ + bool prefer_neon_for_64bits; }; extern const struct tune_params *current_tune; Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 196875) +++ gcc/config/arm/arm.c (revision 196876) @@ -839,6 +839,10 @@ int arm_arch_thumb2; int arm_arch_arm_hwdiv; int arm_arch_thumb_hwdiv; +/* Nonzero if we should use Neon to handle 64-bits operations rather + than core registers. */ +int prefer_neon_for_64bits = 0; + /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we must report the mode of the memory reference from TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */ @@ -936,6 +940,7 @@ const struct tune_params arm_slowmul_tun false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_fastmul_tune = @@ -950,6 +955,7 @@ const struct tune_params arm_fastmul_tun false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; /* StrongARM has early execution of branches, so a sequence that is worth @@ -967,6 +973,7 @@ const struct tune_params arm_strongarm_t false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_xscale_tune = @@ -981,6 +988,7 @@ const struct tune_params arm_xscale_tune false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_9e_tune = @@ -995,6 +1003,7 @@ const struct tune_params arm_9e_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_v6t2_tune = @@ -1009,6 +1018,7 @@ const struct tune_params arm_v6t2_tune = false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ @@ -1024,6 +1034,7 @@ const struct tune_params arm_cortex_tune false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_cortex_a15_tune = @@ -1038,6 +1049,7 @@ const struct tune_params arm_cortex_a15_ true, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is @@ -1055,6 +1067,7 @@ const struct tune_params arm_cortex_a5_t false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_cortex_a9_tune = @@ -1069,6 +1082,7 @@ const struct tune_params arm_cortex_a9_t false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than @@ -1085,6 +1099,7 @@ const struct tune_params arm_v6m_tune = false, /* Prefer LDRD/STRD. */ {false, false}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; const struct tune_params arm_fa726te_tune = @@ -1099,6 +1114,7 @@ const struct tune_params arm_fa726te_tun false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ }; @@ -2129,6 +2145,12 @@ arm_option_override (void) global_options.x_param_values, global_options_set.x_param_values); + /* Use Neon to perform 64-bits operations rather than core + registers. */ + prefer_neon_for_64bits = current_tune->prefer_neon_for_64bits; + if (use_neon_for_64bits == 1) + prefer_neon_for_64bits = true; + /* Use the alternative scheduling-pressure algorithm by default. */ maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2, global_options.x_param_values, Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 196875) +++ gcc/config/arm/arm.h (revision 196876) @@ -354,6 +354,9 @@ extern void (*arm_lang_output_object_att #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) +/* Should NEON be used for 64-bits bitops. */ +#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) + /* True iff the full BPABI is being used. If TARGET_BPABI is true, then TARGET_AAPCS_BASED must be true -- but the converse does not hold. TARGET_BPABI implies the use of the BPABI runtime library, @@ -539,6 +542,10 @@ extern int arm_arch_arm_hwdiv; /* Nonzero if chip supports integer division instruction in Thumb mode. */ extern int arm_arch_thumb_hwdiv; +/* Nonzero if we should use Neon to handle 64-bits operations rather + than core registers. */ +extern int prefer_neon_for_64bits; + #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APCS_FRAME) #endif Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 196875) +++ gcc/config/arm/arm.md (revision 196876) @@ -94,7 +94,7 @@ ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without ; arm_arch6. This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" (const_string "any")) (define_attr "arch_enabled" "no,yes" @@ -129,22 +129,14 @@ (match_test "TARGET_32BIT && !arm_arch6")) (const_string "yes") - (and (eq_attr "arch" "onlya8") - (eq_attr "tune" "cortexa8")) + (and (eq_attr "arch" "avoid_neon_for_64bits") + (match_test "TARGET_NEON") + (not (match_test "TARGET_PREFER_NEON_64BITS"))) (const_string "yes") - (and (eq_attr "arch" "neon_onlya8") - (eq_attr "tune" "cortexa8") - (match_test "TARGET_NEON")) - (const_string "yes") - - (and (eq_attr "arch" "nota8") - (not (eq_attr "tune" "cortexa8"))) - (const_string "yes") - - (and (eq_attr "arch" "neon_nota8") - (not (eq_attr "tune" "cortexa8")) - (match_test "TARGET_NEON")) + (and (eq_attr "arch" "neon_for_64bits") + (match_test "TARGET_NEON") + (match_test "TARGET_PREFER_NEON_64BITS")) (const_string "yes") (and (eq_attr "arch" "iwmmxt2") @@ -4330,7 +4322,7 @@ [(set_attr "length" "*,8,8,*") (set_attr "predicable" "no,yes,yes,no") (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") - (set_attr "arch" "neon_nota8,*,*,neon_onlya8")] + (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] ) (define_expand "one_cmplsi2" @@ -4498,7 +4490,7 @@ "TARGET_32BIT " "#" [(set_attr "length" "8,4,8,8") - (set_attr "arch" "neon_nota8,*,*,neon_onlya8") + (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits") (set_attr "ce_count" "2") (set_attr "predicable" "yes")] ) @@ -4513,7 +4505,7 @@ (set_attr "ce_count" "2") (set_attr "shift" "1") (set_attr "predicable" "yes") - (set_attr "arch" "neon_nota8,*,a,t,neon_onlya8")] + (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")] ) ;; Splits for all extensions to DImode Index: gcc/config/arm/arm.opt =================================================================== --- gcc/config/arm/arm.opt (revision 196875) +++ gcc/config/arm/arm.opt (revision 196876) @@ -247,3 +247,7 @@ that may trigger Cortex-M3 errata. munaligned-access Target Report Var(unaligned_access) Init(2) Enable unaligned word and halfword accesses to packed data. + +mneon-for-64bits +Target Report RejectNegative Var(use_neon_for_64bits) Init(0) +Use Neon to perform 64-bits operations rather than core registers. Index: gcc/config/arm/neon.md =================================================================== --- gcc/config/arm/neon.md (revision 196875) +++ gcc/config/arm/neon.md (revision 196876) @@ -487,7 +487,7 @@ [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*") (set_attr "conds" "*,clob,clob,*,clob,clob,clob") (set_attr "length" "*,8,8,*,8,8,8") - (set_attr "arch" "nota8,*,*,onlya8,*,*,*")] + (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits,*,*,*")] ) (define_insn "*sub3_neon" @@ -524,7 +524,7 @@ [(set_attr "neon_type" "neon_int_2,*,*,*,neon_int_2") (set_attr "conds" "*,clob,clob,clob,*") (set_attr "length" "*,8,8,8,*") - (set_attr "arch" "nota8,*,*,*,onlya8")] + (set_attr "arch" "neon_for_64bits,*,*,*,avoid_neon_for_64bits")] ) (define_insn "*mul3_neon" @@ -699,7 +699,7 @@ } [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") (set_attr "length" "*,*,8,8,*,*") - (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")] + (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] ) ;; The concrete forms of the Neon immediate-logic instructions are vbic and @@ -744,7 +744,7 @@ } [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") (set_attr "length" "*,*,8,8,*,*") - (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")] + (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] ) (define_insn "orn3_neon" @@ -840,7 +840,7 @@ veor\t%P0, %P1, %P2" [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") (set_attr "length" "*,8,8,*") - (set_attr "arch" "nota8,*,*,onlya8")] + (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] ) (define_insn "one_cmpl2" @@ -1162,7 +1162,7 @@ } DONE; }" - [(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8") + [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits") (set_attr "opt" "*,*,speed,speed,*,*")] ) @@ -1263,7 +1263,7 @@ DONE; }" - [(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8") + [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits") (set_attr "opt" "*,*,speed,speed,*,*")] ) Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 196875) +++ gcc/doc/invoke.texi (revision 196876) @@ -510,7 +510,8 @@ Objective-C and Objective-C++ Dialects}. -mtp=@var{name} -mtls-dialect=@var{dialect} @gol -mword-relocations @gol -mfix-cortex-m3-ldrd @gol --munaligned-access} +-munaligned-access @gol +-mneon-for-64bits} @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol @@ -11530,6 +11531,11 @@ setting of this option. If unaligned ac preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be defined. +@item -mneon-for-64bits +@opindex mneon-for-64bits +Enables using Neon to handle scalar 64-bits operations. This is +disabled by default since the cost of moving data from core registers +to Neon is high. @end table @node AVR Options Index: gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c (revision 0) +++ gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c (revision 196876) @@ -0,0 +1,54 @@ +/* Check that Neon is *not* used by default to handle 64-bits scalar + operations. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +typedef long long i64; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef int i32; + +/* Unary operators */ +#define UNARY_OP(name, op) \ + void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } + +/* Binary operators */ +#define BINARY_OP(name, op) \ + void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } + +/* Unsigned shift */ +#define SHIFT_U(name, op, amount) \ + void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } + +/* Signed shift */ +#define SHIFT_S(name, op, amount) \ + void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } + +UNARY_OP(not, ~) + +BINARY_OP(add, +) +BINARY_OP(sub, -) +BINARY_OP(and, &) +BINARY_OP(or, |) +BINARY_OP(xor, ^) + +SHIFT_U(right1, >>, 1) +SHIFT_U(right2, >>, 2) +SHIFT_U(right5, >>, 5) +SHIFT_U(rightn, >>, c) + +SHIFT_S(right1, >>, 1) +SHIFT_S(right2, >>, 2) +SHIFT_S(right5, >>, 5) +SHIFT_S(rightn, >>, c) + +/* { dg-final {scan-assembler-times "vmvn" 0} } */ +/* { dg-final {scan-assembler-times "vadd" 0} } */ +/* { dg-final {scan-assembler-times "vsub" 0} } */ +/* { dg-final {scan-assembler-times "vand" 0} } */ +/* { dg-final {scan-assembler-times "vorr" 0} } */ +/* { dg-final {scan-assembler-times "veor" 0} } */ +/* { dg-final {scan-assembler-times "vshr" 0} } */ Index: gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c (revision 0) +++ gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c (revision 196876) @@ -0,0 +1,57 @@ +/* Check that Neon is used to handle 64-bits scalar operations. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mneon-for-64bits" } */ +/* { dg-add-options arm_neon } */ + +typedef long long i64; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef int i32; + +/* Unary operators */ +#define UNARY_OP(name, op) \ + void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } + +/* Binary operators */ +#define BINARY_OP(name, op) \ + void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } + +/* Unsigned shift */ +#define SHIFT_U(name, op, amount) \ + void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } + +/* Signed shift */ +#define SHIFT_S(name, op, amount) \ + void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } + +UNARY_OP(not, ~) + +BINARY_OP(add, +) +BINARY_OP(sub, -) +BINARY_OP(and, &) +BINARY_OP(or, |) +BINARY_OP(xor, ^) + +SHIFT_U(right1, >>, 1) +SHIFT_U(right2, >>, 2) +SHIFT_U(right5, >>, 5) +SHIFT_U(rightn, >>, c) + +SHIFT_S(right1, >>, 1) +SHIFT_S(right2, >>, 2) +SHIFT_S(right5, >>, 5) +SHIFT_S(rightn, >>, c) + +/* { dg-final {scan-assembler-times "vmvn" 1} } */ +/* Two vadd: 1 in unary_not, 1 in binary_add */ +/* { dg-final {scan-assembler-times "vadd" 2} } */ +/* { dg-final {scan-assembler-times "vsub" 1} } */ +/* { dg-final {scan-assembler-times "vand" 1} } */ +/* { dg-final {scan-assembler-times "vorr" 1} } */ +/* { dg-final {scan-assembler-times "veor" 1} } */ +/* 6 vshr for right shifts by constant, and variable right shift uses + vshl with a negative amount in register. */ +/* { dg-final {scan-assembler-times "vshr" 6} } */ +/* { dg-final {scan-assembler-times "vshl" 2} } */