From patchwork Sun Nov 22 20:38:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Edelsohn X-Patchwork-Id: 547346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AB90E1402A2 for ; Mon, 23 Nov 2015 07:38:34 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=HEzk1sQS; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=hsoCydgRdzwbS/GsbS rQdQreyffTVANLQvykYMGOaj+5O09iHSGjjJ/7Xx4geQ5desCgpjJzPR4N3Fr05A 1/A1Yn3OiHnyZXaDODrTEIm0KCjCXSu+1jzlVrNUSV6MgocJ5bHjGhwcxgNEq3HD ElDxP40LVnpRzevphEe2irFZU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=I7jMMEBKjw8HdUGargoRxl6f IhY=; b=HEzk1sQSYJpqpXbKllW9vSJFHn/+3L5hes5p1yGVDpcX5jj7UTI8opt2 vBmLUK/5fhXaLG1FhW6xvhjrZ9jSet9EAEzhg4WkU8mmppvI65tBo/dfoEZa1mLF p9hkdwtX1EuQEv9BxRKSQ2bp8vT49nNuKCw/x3+lLUoUCjr6BZ8= Received: (qmail 130399 invoked by alias); 22 Nov 2015 20:38:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 130388 invoked by uid 89); 22 Nov 2015 20:38:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lf0-f42.google.com Received: from mail-lf0-f42.google.com (HELO mail-lf0-f42.google.com) (209.85.215.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sun, 22 Nov 2015 20:38:23 +0000 Received: by lfdl133 with SMTP id l133so15390170lfd.2 for ; Sun, 22 Nov 2015 12:38:19 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.25.134.137 with SMTP id i131mr9724425lfd.66.1448224699688; Sun, 22 Nov 2015 12:38:19 -0800 (PST) Received: by 10.114.62.230 with HTTP; Sun, 22 Nov 2015 12:38:19 -0800 (PST) In-Reply-To: References: Date: Sun, 22 Nov 2015 15:38:19 -0500 Message-ID: Subject: Re: [PATCH] lround for PowerPC From: David Edelsohn To: Richard Biener , Segher Boessenkool Cc: "William J. Schmidt" , GCC Patches v2 of the patch. Seems to pass the GCC testsuite, although the testsuite doesn't stress FP. There is something wrong with current VSX SFmode constraints. Index: rs6000.md =================================================================== --- rs6000.md (revision 230723) +++ rs6000.md (working copy) @@ -77,6 +77,7 @@ UNSPEC_FRIN UNSPEC_FRIP UNSPEC_FRIZ + UNSPEC_XSRDPI UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_RELD_MPIC ; re-load_macho_picbase UNSPEC_MPIC_CORRECT ; macho_correct_pic @@ -5500,6 +5501,27 @@ [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_")]) +(define_insn "*xsrdpi2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=wa") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")] + UNSPEC_XSRDPI))] + "TARGET__FPR && TARGET_POPCNTD" + "xsrdpi %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) + +(define_expand "lrounddi2" + [(set (match_dup 2) + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")] + UNSPEC_XSRDPI)) + (set (match_operand:DI 0 "gpc_reg_operand" "=d") + (unspec:DI [(match_dup 2)] + UNSPEC_FCTID))] + "TARGET__FPR && TARGET_POPCNTD" +{ + operands[2] = gen_reg_rtx (mode); +}) + ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" [(set (match_operand:SI 0 "memory_operand" "=Z")