From patchwork Tue Jun 9 17:24:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Edelsohn X-Patchwork-Id: 482314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 604C814075E for ; Wed, 10 Jun 2015 03:24:55 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=U6VEXea2; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=NhseD6jLPJ5g0cpVSrljQddgeSvibaYfh0TR6flVNHpDRD IX6vRv0GkqB8M/qy5RX3HMvgz4691sR7hIbGBZg4/kBVA6Ueq+uYszF06NIm3efM LhgM8LOHRJxVCpDH+zmn933yvXsN2kS6/vIESsl9hlmbuOo/cyQFah4M4snq8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=I8H1xVQUPoXj850V3Sr+csx3nFg=; b=U6VEXea2xFhCB1LSY1wd 5KWbKhMI5izxxT6XzSbGdRzDaIOx8wWDj9Wf2eLVyEMUzxBZWdP33p6i6xldTZVG tNzbl3rFz6XtjBRajfXr2R4i3yKygWcCPDYLC/RsnV2z5RX3y8S0AtXbjK5uZ1gd BFYPhJqgEelg9smUcSwHQck= Received: (qmail 557 invoked by alias); 9 Jun 2015 17:24:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 548 invoked by uid 89); 9 Jun 2015 17:24:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.6 required=5.0 tests=AWL, BAYES_50, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-ig0-f177.google.com Received: from mail-ig0-f177.google.com (HELO mail-ig0-f177.google.com) (209.85.213.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 09 Jun 2015 17:24:44 +0000 Received: by igbsb11 with SMTP id sb11so16383072igb.0 for ; Tue, 09 Jun 2015 10:24:42 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.50.57.39 with SMTP id f7mr21672071igq.35.1433870682425; Tue, 09 Jun 2015 10:24:42 -0700 (PDT) Received: by 10.36.108.21 with HTTP; Tue, 9 Jun 2015 10:24:42 -0700 (PDT) Date: Tue, 9 Jun 2015 13:24:42 -0400 Message-ID: Subject: [PATCH] PowerPC atomic memmodel cleanup From: David Edelsohn To: GCC Patches The infrastructure for atomic operations in the rs6000 port has not utilized the cleaner GCC internal APIs for manipulating memmodel. The appended patch converts the direct casts and use of memmodel_from_int to consistently use memmodel_base. This also allows the SYNC variants to be removed from switch case statements. This should not change any semantics or behavior of atomics in PowerPC code generation. Comments? Bootstrapped on powerpc-ibm-aix7.1.0.0 * config/rs6000/rs6000.c (rs6000_pre_atomic_barrier): Remove SYNC variants cases from switch. (rs6000_post_atomic_barrier): Same. (rs6000_expand_atomic_compare_and_swap): Use memmodel_base. (rs6000_expand_atomic_exchange): Same. (rs6000_expand_atomic_op): Same. * config/rs6000/sync.md (mem_thread_fence): Use memodel_base. Remove SYNC variants cases from switch. (atomic_load): Same. (atomic_store): Same. Thanks, David * config/rs6000/rs6000.c (rs6000_pre_atomic_barrier): Remove SYNC variants cases from switch. (rs6000_post_atomic_barrier): Same. (rs6000_expand_atomic_compare_and_swap): Use memmodel_base. (rs6000_expand_atomic_exchange): Same. (rs6000_expand_atomic_op): Same. * config/rs6000/sync.md (mem_thread_fence): Use memodel_base. Remove SYNC variants cases from switch. (atomic_load): Same. (atomic_store): Same. Index: rs6000.c =================================================================== --- rs6000.c (revision 224288) +++ rs6000.c (working copy) @@ -20558,15 +20558,12 @@ rs6000_pre_atomic_barrier (rtx mem, enum memmodel case MEMMODEL_RELAXED: case MEMMODEL_CONSUME: case MEMMODEL_ACQUIRE: - case MEMMODEL_SYNC_ACQUIRE: break; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_ACQ_REL: emit_insn (gen_lwsync ()); break; case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: emit_insn (gen_hwsync ()); break; default: @@ -20583,13 +20580,10 @@ rs6000_post_atomic_barrier (enum memmodel model) case MEMMODEL_RELAXED: case MEMMODEL_CONSUME: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: break; case MEMMODEL_ACQUIRE: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: emit_insn (gen_isync ()); break; default: @@ -20690,8 +20684,8 @@ rs6000_expand_atomic_compare_and_swap (rtx operand oldval = operands[3]; newval = operands[4]; is_weak = (INTVAL (operands[5]) != 0); - mod_s = memmodel_from_int (INTVAL (operands[6])); - mod_f = memmodel_from_int (INTVAL (operands[7])); + mod_s = memmodel_base (INTVAL (operands[6])); + mod_f = memmodel_base (INTVAL (operands[7])); orig_mode = mode = GET_MODE (mem); mask = shift = NULL_RTX; @@ -20810,7 +20804,7 @@ rs6000_expand_atomic_exchange (rtx operands[]) retval = operands[0]; mem = operands[1]; val = operands[2]; - model = (enum memmodel) INTVAL (operands[3]); + model = memmodel_base (INTVAL (operands[3])); mode = GET_MODE (mem); mask = shift = NULL_RTX; @@ -20861,7 +20855,7 @@ void rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, rtx orig_before, rtx orig_after, rtx model_rtx) { - enum memmodel model = (enum memmodel) INTVAL (model_rtx); + enum memmodel model = memmodel_base (INTVAL (model_rtx)); machine_mode mode = GET_MODE (mem); machine_mode store_mode = mode; rtx label, x, cond, mask, shift; Index: sync.md =================================================================== --- sync.md (revision 224288) +++ sync.md (working copy) @@ -41,7 +41,7 @@ [(match_operand:SI 0 "const_int_operand" "")] ;; model "" { - enum memmodel model = memmodel_from_int (INTVAL (operands[0])); + enum memmodel model = memmodel_base (INTVAL (operands[0])); switch (model) { case MEMMODEL_RELAXED: @@ -48,14 +48,11 @@ break; case MEMMODEL_CONSUME: case MEMMODEL_ACQUIRE: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_ACQ_REL: emit_insn (gen_lwsync ()); break; case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: emit_insn (gen_hwsync ()); break; default: @@ -147,7 +144,7 @@ if (mode == TImode && !TARGET_SYNC_TI) FAIL; - enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + enum memmodel model = memmodel_base (INTVAL (operands[2])); if (is_mm_seq_cst (model)) emit_insn (gen_hwsync ()); @@ -185,9 +182,7 @@ break; case MEMMODEL_CONSUME: case MEMMODEL_ACQUIRE: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: emit_insn (gen_loadsync_ (operands[0])); break; default: @@ -214,17 +209,15 @@ if (mode == TImode && !TARGET_SYNC_TI) FAIL; - enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + enum memmodel model = memmodel_base (INTVAL (operands[2])); switch (model) { case MEMMODEL_RELAXED: break; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: emit_insn (gen_lwsync ()); break; case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: emit_insn (gen_hwsync ()); break; default: