From patchwork Sun Nov 22 01:52:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Edelsohn X-Patchwork-Id: 547273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 05C541401DE for ; Sun, 22 Nov 2015 12:53:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=agTekMHp; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; q=dns; s=default; b=wIRubsoehdICJ0JpXT6sKtDWPjdMYl7RV6l+XBoWQNH 5tNYAzcAtqgNAhOM+0+blLt3eo+1K8LeK6/yA56MjtoqZhN3T2pg73MgCDibtZ/0 0pHY7uk1i5BC15nZ10WCKlptf55CVOVJBQMWJL2xKGcEfV3njJZ8lEXW7+ruK2Fg = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; s=default; bh=+VjjaIg44ZupLb3kJB4M/BZJdqw=; b=agTekMHpUY3T1UlKR gHQDYWal7ImiQ1aiFcwEaC0Hqm9aC3oNYNCD0K0upZFkJj6k+ThuVqfY6vYTG3sY Oi/VXr6BrGZDqHpxX3IWgFIYjxXa2pLScC96+InWdl/KYQYzLcQn5XMhdAfvRXXU BKKIicfINEXY62d+LV3YbNSepo= Received: (qmail 121714 invoked by alias); 22 Nov 2015 01:53:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 121692 invoked by uid 89); 22 Nov 2015 01:52:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f178.google.com Received: from mail-lb0-f178.google.com (HELO mail-lb0-f178.google.com) (209.85.217.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sun, 22 Nov 2015 01:52:57 +0000 Received: by lbblt2 with SMTP id lt2so80190679lbb.3 for ; Sat, 21 Nov 2015 17:52:53 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.112.184.45 with SMTP id er13mr8185295lbc.133.1448157173565; Sat, 21 Nov 2015 17:52:53 -0800 (PST) Received: by 10.114.62.230 with HTTP; Sat, 21 Nov 2015 17:52:53 -0800 (PST) Date: Sat, 21 Nov 2015 20:52:53 -0500 Message-ID: Subject: [PATCH] lround for PowerPC From: David Edelsohn To: Segher Boessenkool , "William J. Schmidt" Cc: GCC Patches PowerPC was missing a definition of the lroundMN pattern, which can be implemented with VSX instructions available in Power7. Below is a first draft. - David * config/rs6000/rs6000.md (*xsrdpidf2): New define_insn. (lrounddfdi2): New define_expand. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8c53c40..eadbe1d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -77,6 +77,7 @@ UNSPEC_FRIN UNSPEC_FRIP UNSPEC_FRIZ + UNSPEC_XSRDPI UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_RELD_MPIC ; re-load_macho_picbase UNSPEC_MPIC_CORRECT ; macho_correct_pic @@ -5245,6 +5246,27 @@ [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_")]) +(define_insn "*xsrdpidf2" + [(set (match_operand:DF 0 "gpc_reg_operand" "=") + (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] + UNSPEC_XSRDPI))] + "TARGET_DF_FPR && TARGET_POPCNTD" + "xsrdpi %0,%1" + [(set_attr "type" "fp")]) + +(define_expand "lrounddfdi2" + [(set (match_dup 2) + (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] + UNSPEC_XSRDPI)) + (set (match_operand:DI 0 "gpc_reg_operand" "=d") + (unspec:DI [(match_dup 2)] + UNSPEC_FCTID))] + "TARGET_DF_FPR && TARGET_POPCNTD + && flag_unsafe_math_optimizations && !flag_trapping_math" +{ + operands[2] = gen_reg_rtx (DFmode); +}) + ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" [(set (match_operand:SI 0 "memory_operand" "=Z")