From patchwork Thu Jan 19 17:13:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 717246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v49R34WS9z9rxv for ; Fri, 20 Jan 2017 04:13:34 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="O9Ld0DK6"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=QYKmn47gbA5vUIC HB3vEktepPlKUjCTSSnOY3tuwVGQDyr+enPHuzMFI60Wfe22N50aYr6Rkr/Rr/TT yO8QbdObKRRTO4Ga+pmhvuDWxeNLTbbGnx8xS7CzH9uDF3BcY6lG41iIfdEGkY0m wTZtP15QoF88f9s7D3xPV+QeJptA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; s=default; bh=wH9+tE3OesiUEobfnBHJJ 5yXHfc=; b=O9Ld0DK6y4roUrvXGP9uA00UNtkwaD+qwF5vq7AcUn/tjdEVSRWZ9 a2keS2QmiNg+nBLMxbT3FpyptdwSv6BMtWVXW1Wi+HqTqNYdpvTiZHGow+YAMz6W 5PFs44FYzPyc8zSz9MyHlCn7DOLap3tv+uRbWX7QvXDwQ45Gqqlibs= Received: (qmail 74498 invoked by alias); 19 Jan 2017 17:13:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73931 invoked by uid 89); 19 Jan 2017 17:13:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=H*f:sk:KLs2Rer, H*i:pCY, H*f:pCY, H*i:sk:KLs2Rer X-HELO: mail-ua0-f193.google.com Received: from mail-ua0-f193.google.com (HELO mail-ua0-f193.google.com) (209.85.217.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 19 Jan 2017 17:13:15 +0000 Received: by mail-ua0-f193.google.com with SMTP id d5so4783474uag.0 for ; Thu, 19 Jan 2017 09:13:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dsYvRVZLpNl8AEFWYJb/ot1+4KkA8v3+DIor44/Lijo=; b=HglzwOkdXc5NOto1xC5A0V6qQnLAGL4QdiCoKk0qAa6x+MtnmuOL04K1FKRdUsKg5m PYsr7+ySiZjWy0dRPYEkr0LPGTHbL/Td/A/7J0gZcQ2Jl3IxVoKkbY7pUdu/TJGH4H45 nlQVgAvBr0bZCWkUOUwXKv3nPDCujD8Vjw5Q6sijm9Mu0Lv8QT0n4EAb6OElbwYYUweO wjtViB2pNOfAvubBlNiEgdPmGvnueMkV7kW5PiPxLFO8EErS3WD5ejQD0qQIU77mhXO6 KDMHd7v3wMBRb0igMA6et7ajBUirk70h9tdURQor7pBfw5evUMfBf2DLuqsAa6B2Acvj Hj8w== X-Gm-Message-State: AIkVDXKl4JxwZZrWUDqxmszvr2gN1Az/DULmtQaDVMfdd4vEN8bAv7h6OG87eXWygw7kbdGHfmYjf4diHAGEsg== X-Received: by 10.159.36.180 with SMTP id 49mr5464448uar.115.1484845994086; Thu, 19 Jan 2017 09:13:14 -0800 (PST) MIME-Version: 1.0 Received: by 10.103.87.11 with HTTP; Thu, 19 Jan 2017 09:13:13 -0800 (PST) In-Reply-To: References: From: Uros Bizjak Date: Thu, 19 Jan 2017 18:13:13 +0100 Message-ID: Subject: Re: [committed] libitm: Disable TSX on processors on which it may be broken. To: "gcc-patches@gcc.gnu.org" Cc: Torvald Riegel , "H. J. Lu" , "Senkevich, Andrew" , Jakub Jelinek On Wed, Jan 18, 2017 at 11:08 PM, Uros Bizjak wrote: > On Wed, Jan 18, 2017 at 10:48 PM, Uros Bizjak wrote: >> Hello! >> >>> This fix follows the same approach that glibc uses to disable TSX on >>> processors on which it is broken. TSX can also be disabled through a >>> microcode update on these processors, but glibc consensus is that it >>> cannot be detected reliably whether the microcode update has been >>> applied. Thus, we just look for affected models/steppings. >>> >>> Tested on x86_64-linux (but I don't have a machine with broken TSX >>> available). >>> >>> libitm/ChangeLog >>> >>> * config/x86/target.h (htm_available): Add check for some processors >>> on which TSX is broken. >> >> + __cpuid (0, a, b, c, d); >> + if (b == 0x756e6547 && c == 0x6c65746e && d == 0x49656e69) >> >> You can use: >> >> #define signature_INTEL_ebx 0x756e6547 >> #define signature_INTEL_ecx 0x6c65746e >> #define signature_INTEL_edx 0x49656e69 >> >> defines from cpuid.h here. > > Actually, just provide a non-NULL second argument to __get_cpuid_max. > It will return %ebx from cpuid, which should be enough to detect Intel > processor. Attached is the patch I have committed to mainline SVN after a short off-line discussion with Torvald. 2017-01-19 Uros Bizjak * config/x86/target.h (htm_available): Determine vendor from __get_cpuid_max return. Use signature_INTEL_ebx. Cleanup. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/x86/target.h =================================================================== --- config/x86/target.h (revision 244636) +++ config/x86/target.h (working copy) @@ -75,31 +75,32 @@ static inline bool htm_available () { const unsigned cpuid_rtm = bit_RTM; - if (__get_cpuid_max (0, NULL) >= 7) + unsigned vendor; + + if (__get_cpuid_max (0, &vendor) >= 7) { unsigned a, b, c, d; - /* TSX is broken on some processors. This can be fixed by microcode, + unsigned family; + + __cpuid (1, a, b, c, d); + family = (a >> 8) & 0x0f; + /* TSX is broken on some processors. TSX can be disabled by microcode, but we cannot reliably detect whether the microcode has been updated. Therefore, do not report availability of TSX on these processors. We use the same approach here as in glibc (see https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html). */ - __cpuid (0, a, b, c, d); - if (b == 0x756e6547 && c == 0x6c65746e && d == 0x49656e69) + if (vendor == signature_INTEL_ebx && family == 0x06) { - __cpuid (1, a, b, c, d); - if (((a >> 8) & 0x0f) == 0x06) // Family. - { - unsigned model = ((a >> 4) & 0x0f) // Model. - + ((a >> 12) & 0xf0); // Extended model. - unsigned stepping = a & 0x0f; - if ((model == 0x3c) - || (model == 0x45) - || (model == 0x46) - /* Xeon E7 v3 has correct TSX if stepping >= 4. */ - || ((model == 0x3f) && (stepping < 4))) - return false; - } + unsigned model = ((a >> 4) & 0x0f) + ((a >> 12) & 0xf0); + unsigned stepping = a & 0x0f; + if (model == 0x3c + /* Xeon E7 v3 has correct TSX if stepping >= 4. */ + || (model == 0x3f && stepping < 4) + || model == 0x45 + || model == 0x46) + return false; } + __cpuid_count (7, 0, a, b, c, d); if (b & cpuid_rtm) return true;