From patchwork Mon Aug 14 16:56:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 801272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-460321-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="KJZxKlKz"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xWMFm2rhzz9s7m for ; Tue, 15 Aug 2017 02:56:28 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=oKDhuFrmzWxtJWKwomb4fDrAylYNQ78VsMMei3cAr1W3cq VDy5Xc+5VgPJ4/qky8Fs1I/Zx/r8hZyxxQSjzpRRCqMH7pVq2EDNsV+CXPm+Mh2b pf2goyCX051Q1mNkN+GAd+gAWRM0pzbR+Knv6/vSayUU1H1ddzG3pyG2x5o58= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=6KW7HEAYWElGyTuhNmDQLLylWv8=; b=KJZxKlKzopPxz4G4L7Rh LUzJGepFN4MLLrgUjlrsSgzC78ulDVVsVNvfNb/nXtA/ysyQhfivrEdgDF+7NQHt FG56IiorBTBMv3srhmQZ01aRQLlmd+XdAobg0ZmoysFmaPXs6uc5sxbOO0kscGwY H74PBi77suF3q+gYWWeyVjA= Received: (qmail 62284 invoked by alias); 14 Aug 2017 16:56:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60848 invoked by uid 89); 14 Aug 2017 16:56:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=hello! X-HELO: mail-vk0-f44.google.com Received: from mail-vk0-f44.google.com (HELO mail-vk0-f44.google.com) (209.85.213.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 14 Aug 2017 16:56:08 +0000 Received: by mail-vk0-f44.google.com with SMTP id g189so33315886vke.5 for ; Mon, 14 Aug 2017 09:56:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=WvbGVBalGhT9/BHKO0FE/wmmM77E8rVxLlQVbzlk67w=; b=oBRjpVu4g4BV4awosVzMV2QIaVG6DirC+5QOBSwuRzqOaJZpjJT2awD9FYe9wi5J5/ WPCLveotc6n+dzn2r6DiXbjStbTSz7HzvOH+zm3BIIIwpHKwEV/E4rE+ZGZNtItGc0nA Qd4fnN2S79FDh5ZxWAh4RRvh882RqR/iVJUVWFtxniIe3fh6g8PDEJf2ozehz4q2VolK HQ/b1efe5wmVvRfgOeWJ7ZEcRKgHvbj1hTnfUruxHDofIgIzratD71uSSER6MWPiZ+6P v4n+yGocJmWjpNg/3lWAo6ZtB0CiXo/TUzt3hiNNYdPS+v3OtkTn3giqrT7Mf6BJkgBp sd1w== X-Gm-Message-State: AHYfb5gs0fXL818p4xAy4a3ZUNqGVhEzwe8vYOOKVQ0U0FJSx9InFdb7 EcKI1F9Q8FQJRMVuoMrrmX69l0+Olg== X-Received: by 10.31.61.198 with SMTP id k189mr16920242vka.134.1502729766832; Mon, 14 Aug 2017 09:56:06 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.68.218 with HTTP; Mon, 14 Aug 2017 09:56:06 -0700 (PDT) From: Uros Bizjak Date: Mon, 14 Aug 2017 18:56:06 +0200 Message-ID: Subject: [PATCH, i386]: Fix PR46091, missed optimization: x86 bt/btc/bts instructions To: "gcc-patches@gcc.gnu.org" Hello! Attached patch implements generation of btr, bts and btc instructions. These insns are generated for operations with registers and exact log2 immediates, where bitpos <= 63 and >= 31. Immediates with bits >= 31 are out of range for x86 andq/orq/xorq instructions, so we save a movabsq constant load. 2017-08-14 Uros Bizjak PR target/46091 * config/i386/i386.md (*anddi_1_btr): New insn_and_split pattern. (*iordi_1_bts): Ditto. (*xordi_1_btc): Ditto. testsuite/ChangeLog: 2017-08-14 Uros Bizjak PR target/46091 * gcc.target/i386/pr46091-1.c: New test. * gcc.target/i386/pr46091-2.c: Ditto. * gcc.target/i386/pr46091-3.c: Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline. Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 251086) +++ config/i386/i386.md (working copy) @@ -8267,6 +8267,27 @@ (const_string "*"))) (set_attr "mode" "SI,DI,DI,SI")]) +(define_insn_and_split "*anddi_1_btr" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI + (match_operand:DI 1 "register_operand" "%0") + (match_operand:DI 2 "const_int_operand" "n"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && TARGET_USE_BT + && IN_RANGE (exact_log2 (~INTVAL (operands[2])), 31, 63)" + "#" + "&& reload_completed" + [(parallel [(set (zero_extract:DI (match_dup 0) + (const_int 1) + (match_dup 3)) + (const_int 0)) + (clobber (reg:CC FLAGS_REG))])] + "operands[3] = GEN_INT (exact_log2 (~INTVAL (operands[2])));" + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "double") + (set_attr "mode" "DI")]) + ;; Turn *anddi_1 into *andsi_1_zext if possible. (define_split [(set (match_operand:DI 0 "register_operand") @@ -8791,6 +8812,50 @@ [(set_attr "type" "alu") (set_attr "mode" "")]) +(define_insn_and_split "*iordi_1_bts" + [(set (match_operand:DI 0 "register_operand" "=r") + (ior:DI + (match_operand:DI 1 "register_operand" "%0") + (match_operand:DI 2 "const_int_operand" "n"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && TARGET_USE_BT + && IN_RANGE (exact_log2 (INTVAL (operands[2])), 31, 63)" + "#" + "&& reload_completed" + [(parallel [(set (zero_extract:DI (match_dup 0) + (const_int 1) + (match_dup 3)) + (const_int 1)) + (clobber (reg:CC FLAGS_REG))])] + "operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2])));" + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "double") + (set_attr "mode" "DI")]) + +(define_insn_and_split "*xordi_1_btc" + [(set (match_operand:DI 0 "register_operand" "=r") + (xor:DI + (match_operand:DI 1 "register_operand" "%0") + (match_operand:DI 2 "const_int_operand" "n"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && TARGET_USE_BT + && IN_RANGE (exact_log2 (INTVAL (operands[2])), 31, 63)" + "#" + "&& reload_completed" + [(parallel [(set (zero_extract:DI (match_dup 0) + (const_int 1) + (match_dup 3)) + (not:DI (zero_extract:DI (match_dup 0) + (const_int 1) + (match_dup 3)))) + (clobber (reg:CC FLAGS_REG))])] + "operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2])));" + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "double") + (set_attr "mode" "DI")]) + ;; See comment for addsi_1_zext why we do use nonimmediate_operand (define_insn "*si_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") Index: testsuite/gcc.target/i386/pr46091-1.c =================================================================== --- testsuite/gcc.target/i386/pr46091-1.c (nonexistent) +++ testsuite/gcc.target/i386/pr46091-1.c (working copy) @@ -0,0 +1,9 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +unsigned long long test (unsigned long long a) +{ + return a & ~(1ull << 55); +} + +/* { dg-final { scan-assembler "btr" } } */ Index: testsuite/gcc.target/i386/pr46091-2.c =================================================================== --- testsuite/gcc.target/i386/pr46091-2.c (nonexistent) +++ testsuite/gcc.target/i386/pr46091-2.c (working copy) @@ -0,0 +1,9 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +unsigned long long test (unsigned long long a) +{ + return a | (1ull << 55); +} + +/* { dg-final { scan-assembler "bts" } } */ Index: testsuite/gcc.target/i386/pr46091-3.c =================================================================== --- testsuite/gcc.target/i386/pr46091-3.c (nonexistent) +++ testsuite/gcc.target/i386/pr46091-3.c (working copy) @@ -0,0 +1,9 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +unsigned long long test (unsigned long long a) +{ + return a ^ (1ull << 55); +} + +/* { dg-final { scan-assembler "btc" } } */