From patchwork Fri Aug 16 14:32:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1148259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507130-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="MGDtk8ov"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="U9fBhjjk"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4695Qs0dNJz9sML for ; Sat, 17 Aug 2019 00:33:24 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=QTSTcJPpqy8+I+7WPUHJaALThIf0NonmevlN1/DLGbun10 ZL3zWwjbtIpB1DSfaokygUhw7CYo3zZgPLba7rQ0vvDrkhZ8Akf49xjEUARjwns3 ZzGuQakIn/gAUetANMpp+0lfnCOrjIVoaDvK1xjMVmxLfoQrlGAUoTVtv0NiY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=X3t3Jr+szdC3GfpT+yMP2Rp1ZSI=; b=MGDtk8ovMbw25/5bGjVD e1jxoWumtBQllv6ECnl7j/Eh0LMEy3kd+sEpjMFiPKLIJYAOR9LLd/IoXWZCyYfp CMfPPI+RYBDzdumQlGyw1uswJOQAVNqF3YzAc/H0whXutrR02G5BV/cqNTxxeXVC YO5uD0M7o9zgL6z9mAwXwyM= Received: (qmail 73605 invoked by alias); 16 Aug 2019 14:33:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73504 invoked by uid 89); 16 Aug 2019 14:33:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=lshiftrt, const1_rtx, CONST1_RTX, 3_ceil X-HELO: mail-io1-f42.google.com Received: from mail-io1-f42.google.com (HELO mail-io1-f42.google.com) (209.85.166.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Aug 2019 14:33:16 +0000 Received: by mail-io1-f42.google.com with SMTP id i22so6561971ioh.2 for ; Fri, 16 Aug 2019 07:33:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=+7zhVflPX1r0JghCo/MtkgoLebD4/s35oLvp9jo4gso=; b=U9fBhjjk2Y1ndLKfV1cNAWQeQNosQTzVRHkqjSBgR6CysEAFFk/dxz6IcDiq1HDLoy nNnoOFy8giWfzyTQcJeQDs568q+rtRvwp2vPQPRMrsNXSJYHPxDoZSU57mYAEYdoJzJd bmRAeBaYvQrY5Z33PunVPIVzRFjDr5/Np2aoz9LXrPfH5b4fd3Ws38XiqK/p5NSQi5mJ KLvRthHcXgudr5vhB3Tz2gbqj4jTmy6lVhkT29X21v4pyNsq+fWyynesLGiO8sIAWLUK 5cGInxr9fVgUpNhp+c4j6ug1JSQj4mVSuAT9qtyUfpsknR715zNtW6vS4yeIGYo/Y94g XRpQ== MIME-Version: 1.0 From: Uros Bizjak Date: Fri, 16 Aug 2019 16:32:45 +0200 Message-ID: Subject: [PATCH, i386]: Introduce uavg3_ceil for 64bit MMX modes To: "gcc-patches@gcc.gnu.org" Attached patch introduces uavg3_ceil for V8QI and V4HI modes for TARGET_MMX_WITH_SSE targets. Also, the patch fixes invalid RTX generation for SSE and AVX uavg3 patterns. 2019-08-16 Uroš Bizjak * config/i386/mmx.md (mmxdoublemode): New mode attribute. (mmx_uavg3): Macroize expaner from mmx_uavgv8qi3 and mmx_uavgv4hi3 using MMXMODE12 mode iterator. (uavg3_ceil): New expander. * config/i386/sse.md (uavg3_ceil): Use ssedoublemode mode iterator when creating CONST1_RTX. (_uavg3): Ditto. (*_uavg3): Use ssedoublemode mode iterator for const1_operand predicate. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/mmx.md =================================================================== --- config/i386/mmx.md (revision 274564) +++ config/i386/mmx.md (working copy) @@ -58,6 +58,9 @@ ;; Mapping from integer vector mode to mnemonic suffix (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (V1DI "q")]) +(define_mode_attr mmxdoublemode + [(V8QI "V8HI") (V4HI "V4SI")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Move patterns @@ -1948,24 +1951,24 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "mmx_uavgv8qi3" - [(set (match_operand:V8QI 0 "register_operand") - (truncate:V8QI - (lshiftrt:V8HI - (plus:V8HI - (plus:V8HI - (zero_extend:V8HI - (match_operand:V8QI 1 "register_mmxmem_operand")) - (zero_extend:V8HI - (match_operand:V8QI 2 "register_mmxmem_operand"))) - (const_vector:V8HI [(const_int 1) (const_int 1) - (const_int 1) (const_int 1) - (const_int 1) (const_int 1) - (const_int 1) (const_int 1)])) +(define_expand "mmx_uavg3" + [(set (match_operand:MMXMODE12 0 "register_operand") + (truncate:MMXMODE12 + (lshiftrt: + (plus: + (plus: + (zero_extend: + (match_operand:MMXMODE12 1 "register_mmxmem_operand")) + (zero_extend: + (match_operand:MMXMODE12 2 "register_mmxmem_operand"))) + (match_dup 3)) (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW)" - "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);") +{ + operands[3] = CONST1_RTX(mode); + ix86_fixup_binary_operands_no_copy (PLUS, mode, operands); +}) (define_insn "*mmx_uavgv8qi3" [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") @@ -1984,7 +1987,7 @@ (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW) - && ix86_binary_operator_ok (PLUS, V8QImode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { switch (which_alternative) { @@ -2013,23 +2016,6 @@ (const_string "*"))) (set_attr "mode" "DI,TI,TI")]) -(define_expand "mmx_uavgv4hi3" - [(set (match_operand:V4HI 0 "register_operand") - (truncate:V4HI - (lshiftrt:V4SI - (plus:V4SI - (plus:V4SI - (zero_extend:V4SI - (match_operand:V4HI 1 "register_mmxmem_operand")) - (zero_extend:V4SI - (match_operand:V4HI 2 "register_mmxmem_operand"))) - (const_vector:V4SI [(const_int 1) (const_int 1) - (const_int 1) (const_int 1)])) - (const_int 1))))] - "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && (TARGET_SSE || TARGET_3DNOW_A)" - "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);") - (define_insn "*mmx_uavgv4hi3" [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI @@ -2045,7 +2031,7 @@ (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A) - && ix86_binary_operator_ok (PLUS, V4HImode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pavgw\t{%2, %0|%0, %2} pavgw\t{%2, %0|%0, %2} @@ -2055,6 +2041,24 @@ (set_attr "type" "mmxshft,sseiadd,sseiadd") (set_attr "mode" "DI,TI,TI")]) +(define_expand "uavg3_ceil" + [(set (match_operand:MMXMODE12 0 "register_operand") + (truncate:MMXMODE12 + (lshiftrt: + (plus: + (plus: + (zero_extend: + (match_operand:MMXMODE12 1 "register_operand")) + (zero_extend: + (match_operand:MMXMODE12 2 "register_operand"))) + (match_dup 3)) + (const_int 1))))] + "TARGET_MMX_WITH_SSE" +{ + operands[3] = CONST1_RTX(mode); + ix86_fixup_binary_operands_no_copy (PLUS, mode, operands); +}) + (define_insn "mmx_psadbw" [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv") (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0,0,Yv") Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 274564) +++ config/i386/sse.md (working copy) @@ -11900,7 +11900,7 @@ (const_int 1))))] "TARGET_SSE2" { - operands[3] = CONST1_RTX(mode); + operands[3] = CONST1_RTX(mode); ix86_fixup_binary_operands_no_copy (PLUS, mode, operands); }) @@ -15641,7 +15641,7 @@ (const_int 1))))] "TARGET_SSE2 && && " { - operands[] = CONST1_RTX(mode); + operands[] = CONST1_RTX(mode); ix86_fixup_binary_operands_no_copy (PLUS, mode, operands); }) @@ -15655,7 +15655,7 @@ (match_operand:VI12_AVX2 1 "vector_operand" "%0,v")) (zero_extend: (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm"))) - (match_operand:VI12_AVX2 "const1_operand")) + (match_operand: "const1_operand")) (const_int 1))))] "TARGET_SSE2 && && && !(MEM_P (operands[1]) && MEM_P (operands[2]))"