diff mbox series

i386: Rename index_register_operand predicate to register_no_SP_operand

Message ID CAFULd4a_eva9FnxD1y4Qp6HnQ3DMr+MKkCnQaKBrXJw4D+=_Hw@mail.gmail.com
State New
Headers show
Series i386: Rename index_register_operand predicate to register_no_SP_operand | expand

Commit Message

Uros Bizjak May 5, 2023, 1:16 p.m. UTC 
Rename index_register_operand predicate to what it really does.

No functional change.

gcc/ChangeLog:

    * config/i386/predicates.md (register_no_SP_operand):
    Rename from index_register_operand.
    (call_register_operand): Update for rename.
    * config/i386/i386.md (*lea<mode>_general_[1234]): Update for rename.

Bootstrapped on x86_64-linux-gnu.

Pushed to master.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 63207fc9305..cf90867b801 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7068,7 +7068,7 @@  (define_expand "uaddv<mode>4"
 (define_insn_and_split "*lea<mode>_general_1"
   [(set (match_operand:SWI12 0 "register_operand" "=r")
 	(plus:SWI12
-	  (plus:SWI12 (match_operand:SWI12 1 "index_register_operand" "l")
+	  (plus:SWI12 (match_operand:SWI12 1 "register_no_SP_operand" "l")
 		      (match_operand:SWI12 2 "register_operand" "r"))
 	  (match_operand:SWI12 3 "immediate_operand" "i")))]
   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
@@ -7090,7 +7090,7 @@  (define_insn_and_split "*lea<mode>_general_1"
 (define_insn_and_split "*lea<mode>_general_2"
   [(set (match_operand:SWI12 0 "register_operand" "=r")
 	(plus:SWI12
-	  (mult:SWI12 (match_operand:SWI12 1 "index_register_operand" "l")
+	  (mult:SWI12 (match_operand:SWI12 1 "register_no_SP_operand" "l")
 		      (match_operand 2 "const248_operand" "n"))
 	  (match_operand:SWI12 3 "nonmemory_operand" "ri")))]
   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
@@ -7111,7 +7111,7 @@  (define_insn_and_split "*lea<mode>_general_2"
 (define_insn_and_split "*lea<mode>_general_2b"
   [(set (match_operand:SWI12 0 "register_operand" "=r")
 	(plus:SWI12
-	  (ashift:SWI12 (match_operand:SWI12 1 "index_register_operand" "l")
+	  (ashift:SWI12 (match_operand:SWI12 1 "register_no_SP_operand" "l")
 			(match_operand 2 "const123_operand" "n"))
 	  (match_operand:SWI12 3 "nonmemory_operand" "ri")))]
   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
@@ -7133,7 +7133,7 @@  (define_insn_and_split "*lea<mode>_general_3"
   [(set (match_operand:SWI12 0 "register_operand" "=r")
 	(plus:SWI12
 	  (plus:SWI12
-	    (mult:SWI12 (match_operand:SWI12 1 "index_register_operand" "l")
+	    (mult:SWI12 (match_operand:SWI12 1 "register_no_SP_operand" "l")
 			(match_operand 2 "const248_operand" "n"))
 	    (match_operand:SWI12 3 "register_operand" "r"))
 	  (match_operand:SWI12 4 "immediate_operand" "i")))]
@@ -7159,7 +7159,7 @@  (define_insn_and_split "*lea<mode>_general_3b"
   [(set (match_operand:SWI12 0 "register_operand" "=r")
 	(plus:SWI12
 	  (plus:SWI12
-	    (ashift:SWI12 (match_operand:SWI12 1 "index_register_operand" "l")
+	    (ashift:SWI12 (match_operand:SWI12 1 "register_no_SP_operand" "l")
 			  (match_operand 2 "const123_operand" "n"))
 	    (match_operand:SWI12 3 "register_operand" "r"))
 	  (match_operand:SWI12 4 "immediate_operand" "i")))]
@@ -7185,7 +7185,7 @@  (define_insn_and_split "*lea<mode>_general_4"
   [(set (match_operand:SWI12 0 "register_operand" "=r")
 	(any_or:SWI12
 	  (ashift:SWI12
-	    (match_operand:SWI12 1 "index_register_operand" "l")
+	    (match_operand:SWI12 1 "register_no_SP_operand" "l")
 	    (match_operand 2 "const_0_to_3_operand"))
 	  (match_operand 3 "const_int_operand")))]
   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
@@ -7209,7 +7209,7 @@  (define_insn_and_split "*lea<mode>_general_4"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
 	(any_or:SWI48
 	  (ashift:SWI48
-	    (match_operand:SWI48 1 "index_register_operand" "l")
+	    (match_operand:SWI48 1 "register_no_SP_operand" "l")
 	    (match_operand 2 "const_0_to_3_operand"))
 	  (match_operand 3 "const_int_operand")))]
   "(unsigned HOST_WIDE_INT) INTVAL (operands[3])
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 362266e1f6c..fb07707dcba 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -711,7 +711,7 @@  (define_predicate "register_no_elim_operand"
 
 ;; Similarly, but include the stack pointer.  This is used
 ;; to prevent esp from being used as an index reg.
-(define_predicate "index_register_operand"
+(define_predicate "register_no_SP_operand"
   (match_operand 0 "register_operand")
 {
   if (SUBREG_P (op))
@@ -735,7 +735,7 @@  (define_predicate "index_register_operand"
 (define_predicate "call_register_operand"
   (if_then_else (match_test "TARGET_64BIT")
     (match_operand 0 "register_operand")
-    (match_operand 0 "index_register_operand")))
+    (match_operand 0 "register_no_SP_operand")))
 
 ;; Return false if this is any eliminable register.  Otherwise general_operand.
 (define_predicate "general_no_elim_operand"