From patchwork Fri Dec 28 22:53:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1019269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-493171-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="J/4C8UIi"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="c+/0AglK"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43RMSY4QPbz9s55 for ; Sat, 29 Dec 2018 09:53:31 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=MBzjwcdXCSphMGEhiJUS29V16WYjpjeIicnNrELR8HANLf DtJ0keBOzn4bpD0u7cF9BK78kpEPBoc3oSMzSS0YtZHvJ0LlCqfU6vG0fzJjJc1q TEJw0prc+Y7onDCPzWW93wG3PNGeTy6vkC9LaIbTrpRJWBDXFAnfCT865+EUU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=7CrR1FvL4nVxQCdOnIRtLm+zeP4=; b=J/4C8UIiNm+kiExWMWHb GGnIDEQMUCg339FG4kCeHq3t21QxZ/+C8s9aGMIywgUdRZqJX8MtgIJbYpeL2/sV s78FDWVxr3LoailOiDxUBVxVLHbjVGPKJT3DN8bmYa1Z43dC8VIQr0BAvbR7/gPr 8L1VPJnEUfoDoGhefAfnnMk= Received: (qmail 78647 invoked by alias); 28 Dec 2018 22:53:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 78638 invoked by uid 89); 28 Dec 2018 22:53:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-io1-f50.google.com Received: from mail-io1-f50.google.com (HELO mail-io1-f50.google.com) (209.85.166.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 28 Dec 2018 22:53:22 +0000 Received: by mail-io1-f50.google.com with SMTP id t24so17771970ioi.0 for ; Fri, 28 Dec 2018 14:53:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=HzmrsFbwHIkstA4Flcg+9t0ys5hExPewt5YLhOqI+20=; b=c+/0AglKg5LeFrAKWbXctt9I6tYbK9XuJ2DHYDKqRjToxpzCBLLI77+6HThBxSqocT xA/5xV3xh/o6OH+RcRfbypJCSRL+yj6HXUeYt9gDfmpwthRT7iabRXHHI8lzf9RnKlD/ 5P4nBlT4nH3moYsbltYN/3hSZwMpnry7yDs0XNWh91L+u886EQv28DxGqN37FipThJBo /l0CrVesvnlR4aRyTRIBctlz4bIJHEeT+vzz7RBleODEKVTjHeBImM2qbInPuEpV9IKo FeD2oAFMiQmCgOUkvqwbl8HY3Tvo7ZBcKUXRmg6XWpbPLXcuN8eiFCMmjte6Hyb2gHux SKsw== MIME-Version: 1.0 From: Uros Bizjak Date: Fri, 28 Dec 2018 23:53:08 +0100 Message-ID: Subject: [PATCH, i386]: Add some missing QImode register aliases to ADDITIONAL_REGISTER_NAMES To: "gcc-patches@gcc.gnu.org" 2018-12-28 Uros Bizjak * config/i386/i386.h (ADDITIONAL_REGISTER_NAMES): Add sil, dil, bpl and spl aliases. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: i386.h =================================================================== --- i386.h (revision 267418) +++ i386.h (working copy) @@ -2041,6 +2041,12 @@ #define REGISTER_NAMES HI_REGISTER_NAMES +#define QI_REGISTER_NAMES \ +{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"} + +#define QI_HIGH_REGISTER_NAMES \ +{"ah", "dh", "ch", "bh"} + /* Table of additional register names to use in user input. */ #define ADDITIONAL_REGISTER_NAMES \ @@ -2050,6 +2056,7 @@ { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \ { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \ { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \ + { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \ { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \ { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \ { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \ @@ -2069,20 +2076,6 @@ { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \ } -/* Note we are omitting these since currently I don't know how -to get gcc to use these, since they want the same but different -number as al, and ax. -*/ - -#define QI_REGISTER_NAMES \ -{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} - -/* These parallel the array above, and can be used to access bits 8:15 - of regs 0 through 3. */ - -#define QI_HIGH_REGISTER_NAMES \ -{"ah", "dh", "ch", "bh", } - /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(N) \