From patchwork Thu May 27 12:49:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1484576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=MhILghV6; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FrSLr0YQsz9sVt for ; Thu, 27 May 2021 22:49:23 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B0B73858025; Thu, 27 May 2021 12:49:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8B0B73858025 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1622119759; bh=VIPiLrMP/JpfgeBy4M/PBU9w/v4eDXoYJH/x4jCrndU=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=MhILghV6aNvl/wBm8XlzWhAZu8k/EF4acivhm67GR9tLgFZ8hqJ2RQMsKuHWYJpLy dSfL38q6IW4DAAHsmBBiR3qEKxDCmgu7waEPqY1KHs4lfUfhyn0NjJ+WMZmQtVwVTF 4b9Ait0g7UBV/Hxa9LTW+v3dxEkx5j9IcicnVPlY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by sourceware.org (Postfix) with ESMTPS id 188F13858023 for ; Thu, 27 May 2021 12:49:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 188F13858023 Received: by mail-qv1-xf2d.google.com with SMTP id u33so2483054qvf.9 for ; Thu, 27 May 2021 05:49:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=VIPiLrMP/JpfgeBy4M/PBU9w/v4eDXoYJH/x4jCrndU=; b=gV2+z0XVH10iVz/CMfBhRB5wQMaY0FLdGws4AZvF1M7JiveHBvSJPBl2DVmhuDHayq pktboxXTZW8mKt4KFZI9WOruljRE4bFcqoTx2JrzGDvsO2dhbdWc3b53pvg9LBylI2xL AkCsyeXOdtlVEBEJs4XbXOIr2o6Q4iVPzVRepJ0thjs/fLSmHYFo9h02z8VzSsAZ55Ml 1d5lvgXU6ba1DmI1s2ESbNcfqfWh689PpUOxIN72RcdwIu0EvaIGg1380CFAZqpgWwBN 4P/RDIa+h1oEm+LAGrpR2HISO2cBAdj+DdBfSHMzhkkqZOQFQLUlxGFFK0C608nK7gXH tLlg== X-Gm-Message-State: AOAM531gQ89dQzYs7hktVOW0h3lZAcCoyF+WydbSy/oGiXTrHtabJciD vfEsj06ngZwb50rlPl847D7CjIfLiAEzkfKT+WVQWTBqDZyTKg== X-Google-Smtp-Source: ABdhPJzAYp6FcQXwC32vv+/7DNlowXyRtOoAZ5/lozFEhvu+kS7gp5DSr309f1LfEIluf0VIZIDmZHv+li3BTnGzQrg= X-Received: by 2002:a05:6214:b61:: with SMTP id ey1mr3653663qvb.30.1622119754953; Thu, 27 May 2021 05:49:14 -0700 (PDT) MIME-Version: 1.0 Date: Thu, 27 May 2021 14:49:03 +0200 Message-ID: Subject: [PATCH] i386: Add XOP comparisons for 4- and 8-byte vectors [PR100637] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" 2021-05-27 Uroš Bizjak gcc/ PR target/100637 * config/i386/i386-expand.c (ix86_expand_int_sse_cmp): For TARGET_XOP bypass SSE comparisons for all supported vector modes. * config/i386/mmx.md (*xop_maskcmp3): New insn pattern. (*xop_maskcmp3): Ditto. (*xop_maskcmp_uns3): Ditto. (*xop_maskcmp_uns3): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 931b3362144..4185f58eed5 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -4124,8 +4124,8 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, /* XOP supports all of the comparisons on all 128-bit vector int types. */ if (TARGET_XOP - && (mode == V16QImode || mode == V8HImode - || mode == V4SImode || mode == V2DImode)) + && GET_MODE_CLASS (mode) == MODE_VECTOR_INT + && GET_MODE_SIZE (mode) <= 16) ; /* AVX512F supports all of the comparsions on all 128/256/512-bit vector int types. */ diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 23d88a4c265..35e4123fa25 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2121,6 +2121,62 @@ (define_insn "*gt3" (set_attr "type" "ssecmp") (set_attr "mode" "TI")]) +(define_insn "*xop_maskcmp3" + [(set (match_operand:MMXMODEI 0 "register_operand" "=x") + (match_operator:MMXMODEI 1 "ix86_comparison_int_operator" + [(match_operand:MMXMODEI 2 "register_operand" "x") + (match_operand:MMXMODEI 3 "register_operand" "x")]))] + "TARGET_XOP" + "vpcom%Y1\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "sse4arg") + (set_attr "prefix_data16" "0") + (set_attr "prefix_rep" "0") + (set_attr "prefix_extra" "2") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + +(define_insn "*xop_maskcmp3" + [(set (match_operand:VI_32 0 "register_operand" "=x") + (match_operator:VI_32 1 "ix86_comparison_int_operator" + [(match_operand:VI_32 2 "register_operand" "x") + (match_operand:VI_32 3 "register_operand" "x")]))] + "TARGET_XOP" + "vpcom%Y1\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "sse4arg") + (set_attr "prefix_data16" "0") + (set_attr "prefix_rep" "0") + (set_attr "prefix_extra" "2") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + +(define_insn "*xop_maskcmp_uns3" + [(set (match_operand:MMXMODEI 0 "register_operand" "=x") + (match_operator:MMXMODEI 1 "ix86_comparison_uns_operator" + [(match_operand:MMXMODEI 2 "register_operand" "x") + (match_operand:MMXMODEI 3 "register_operand" "x")]))] + "TARGET_XOP" + "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "ssecmp") + (set_attr "prefix_data16" "0") + (set_attr "prefix_rep" "0") + (set_attr "prefix_extra" "2") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + +(define_insn "*xop_maskcmp_uns3" + [(set (match_operand:VI_32 0 "register_operand" "=x") + (match_operator:VI_32 1 "ix86_comparison_uns_operator" + [(match_operand:VI_32 2 "register_operand" "x") + (match_operand:VI_32 3 "register_operand" "x")]))] + "TARGET_XOP" + "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "ssecmp") + (set_attr "prefix_data16" "0") + (set_attr "prefix_rep" "0") + (set_attr "prefix_extra" "2") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + (define_expand "vec_cmp" [(set (match_operand:MMXMODEI 0 "register_operand") (match_operator:MMXMODEI 1 ""