From patchwork Tue Mar 19 07:40:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 228946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 437632C00B8 for ; Tue, 19 Mar 2013 19:24:13 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=dkim1; b=f6H/1iBTy/BNRL+V82iL9ZqrXR0lIeYjN2TEBV1OGMdt2B+L F6VwFHkS3HAyYAFllhBmkf/2eleDCuHAGNTfqmQ752TV7CjAfmEA90+18D2RM+0b HKU6kPRdJ6tXPczBO7L0Oxams71LSnM6r5G6YDU+DaVnw4kEV3tAdF6+Zxk= DKIM-Signature: v=1; a=rsa-sha1; c=simple; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= dkim1; bh=0AjIj80gdNFhgdd/lmimt5WSVog=; b=aRcEszUvKOck1OATT1wUGr AhvlIZApnV3DiwZwgLIzw6VXO8O9arZnI2QE/AH1PMjKf1bcOwil+MLTQKjymxjW BAbb9y1gqTrLKr/s1vfmPxJu2dmiOababuAnpU2PcqySG0j4ShThdVe0rEV6e2Xm KuYnFrDCNiRkfmzH+sb0E= Received: (qmail 5723 invoked by alias); 19 Mar 2013 07:59:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3382 invoked by uid 89); 19 Mar 2013 07:40:05 -0000 Received: from mail-oa0-f54.google.com (HELO mail-oa0-f54.google.com) (209.85.219.54) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 19 Mar 2013 07:40:05 +0000 Received: by mail-oa0-f54.google.com with SMTP id n12so142211oag.27 for ; Tue, 19 Mar 2013 00:40:04 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.171.230 with SMTP id ax6mr599289oec.25.1363678804697; Tue, 19 Mar 2013 00:40:04 -0700 (PDT) Received: by 10.182.49.68 with HTTP; Tue, 19 Mar 2013 00:40:04 -0700 (PDT) Date: Tue, 19 Mar 2013 08:40:04 +0100 Message-ID: Subject: [PATCH 2/n, i386]: Merge TImode and DImode move patterns From: Uros Bizjak To: gcc-patches@gcc.gnu.org Hello! Attached patch merges TImode and DImode move patterns using x64 and nox64 isa attributes. 2013-03-19 Uros Bizjak * config/i386/i386.md (*movti_internal): Merge from *movti_internal_rex64 and *movti_internal_sse. Use x64 isa attribute. (*movdi_internal): Merge with *movdi_internal_rex64. Use x64 and nox64 isa attributes. Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline. Uros. Index: i386.md =================================================================== --- i386.md (revision 196757) +++ i386.md (working copy) @@ -1656,6 +1656,40 @@ ;; Move instructions. +;; Reload patterns to support multi-word load/store +;; with non-offsetable address. +(define_expand "reload_noff_store" + [(parallel [(match_operand 0 "memory_operand" "=m") + (match_operand 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "=&r")])] + "TARGET_64BIT" +{ + rtx mem = operands[0]; + rtx addr = XEXP (mem, 0); + + emit_move_insn (operands[2], addr); + mem = replace_equiv_address_nv (mem, operands[2]); + + emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1])); + DONE; +}) + +(define_expand "reload_noff_load" + [(parallel [(match_operand 0 "register_operand" "=r") + (match_operand 1 "memory_operand" "m") + (match_operand:DI 2 "register_operand" "=r")])] + "TARGET_64BIT" +{ + rtx mem = operands[1]; + rtx addr = XEXP (mem, 0); + + emit_move_insn (operands[2], addr); + mem = replace_equiv_address_nv (mem, operands[2]); + + emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem)); + DONE; +}) + (define_expand "movoi" [(set (match_operand:OI 0 "nonimmediate_operand") (match_operand:OI 1 "general_operand"))] @@ -1760,10 +1794,11 @@ ] (const_string "OI")))]) -(define_insn "*movti_internal_rex64" +(define_insn "*movti_internal" [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,x,x ,m") (match_operand:TI 1 "general_operand" "riFo,re,C,xm,x"))] - "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "(TARGET_64BIT || TARGET_SSE) + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (which_alternative) { @@ -1795,12 +1830,14 @@ gcc_unreachable (); } } - [(set_attr "type" "*,*,sselog1,ssemov,ssemov") + [(set_attr "isa" "x64,x64,*,*,*") + (set_attr "type" "*,*,sselog1,ssemov,ssemov") (set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex") (set (attr "mode") (cond [(eq_attr "alternative" "0,1") (const_string "DI") - (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (ior (not (match_test "TARGET_SSE2")) + (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) (const_string "V4SF") (and (eq_attr "alternative" "4") (match_test "TARGET_SSE_TYPELESS_STORES")) @@ -1820,82 +1857,21 @@ [(const_int 0)] "ix86_split_long_move (operands); DONE;") -(define_insn "*movti_internal_sse" - [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x ,m") - (match_operand:TI 1 "vector_move_operand" "C ,xm,x"))] - "TARGET_SSE && !TARGET_64BIT - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" -{ - switch (which_alternative) - { - case 0: - return standard_sse_constant_opcode (insn, operands[1]); - case 1: - case 2: - /* TDmode values are passed as TImode on the stack. Moving them - to stack may result in unaligned memory access. */ - if (misaligned_operand (operands[0], TImode) - || misaligned_operand (operands[1], TImode)) - { - if (get_attr_mode (insn) == MODE_V4SF) - return "%vmovups\t{%1, %0|%0, %1}"; - else - return "%vmovdqu\t{%1, %0|%0, %1}"; - } - else - { - if (get_attr_mode (insn) == MODE_V4SF) - return "%vmovaps\t{%1, %0|%0, %1}"; - else - return "%vmovdqa\t{%1, %0|%0, %1}"; - } - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sselog1,ssemov,ssemov") - (set_attr "prefix" "maybe_vex") - (set (attr "mode") - (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") - (const_string "V4SF") - (and (eq_attr "alternative" "2") - (match_test "TARGET_SSE_TYPELESS_STORES")) - (const_string "V4SF") - (match_test "TARGET_AVX") - (const_string "TI") - (ior (not (match_test "TARGET_SSE2")) - (match_test "optimize_function_for_size_p (cfun)")) - (const_string "V4SF") - ] - (const_string "TI")))]) - -(define_insn "*movdi_internal_rex64" +(define_insn "*movdi_internal" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r,r ,r,m ,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym") + "=r ,o ,r,r ,r,m ,*y,m*y,*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym") (match_operand:DI 1 "general_operand" - "Z ,rem,i,re,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))] - "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "riFo,riF,Z,rem,i,re,C ,*y ,m ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))] + "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) { - case TYPE_SSECVT: - if (SSE_REG_P (operands[0])) - return "movq2dq\t{%1, %0|%0, %1}"; - else - return "movdq2q\t{%1, %0|%0, %1}"; + case TYPE_MULTI: + return "#"; - case TYPE_SSEMOV: - if (get_attr_mode (insn) == MODE_V4SF) - return "%vmovaps\t{%1, %0|%0, %1}"; - else if (get_attr_mode (insn) == MODE_TI) - return "%vmovdqa\t{%1, %0|%0, %1}"; + case TYPE_MMX: + return "pxor\t%0, %0"; - /* Handle broken assemblers that require movd instead of movq. */ - if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])) - return "%vmovd\t{%1, %0|%0, %1}"; - else - return "%vmovq\t{%1, %0|%0, %1}"; - case TYPE_MMXMOV: /* Handle broken assemblers that require movd instead of movq. */ if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])) @@ -1906,9 +1882,28 @@ case TYPE_SSELOG1: return standard_sse_constant_opcode (insn, operands[1]); - case TYPE_MMX: - return "pxor\t%0, %0"; + case TYPE_SSEMOV: + switch (get_attr_mode (insn)) + { + case MODE_DI: + return "%vmovq\t{%1, %0|%0, %1}"; + case MODE_TI: + return "%vmovdqa\t{%1, %0|%0, %1}"; + case MODE_V4SF: + return "%vmovaps\t{%1, %0|%0, %1}"; + case MODE_V2SF: + gcc_assert (!TARGET_AVX); + return "movlps\t{%1, %0|%0, %1}"; + default: + gcc_unreachable (); + } + case TYPE_SSECVT: + if (SSE_REG_P (operands[0])) + return "movq2dq\t{%1, %0|%0, %1}"; + else + return "movdq2q\t{%1, %0|%0, %1}"; + case TYPE_LEA: return "lea{q}\t{%E1, %0|%0, %E1}"; @@ -1916,7 +1911,7 @@ gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1])); if (get_attr_mode (insn) == MODE_SI) return "mov{l}\t{%k1, %k0|%k0, %k1}"; - else if (which_alternative == 2) + else if (which_alternative == 4) return "movabs{q}\t{%1, %0|%0, %1}"; else if (ix86_use_lea_for_mov (insn, operands)) return "lea{q}\t{%E1, %0|%0, %E1}"; @@ -1924,16 +1919,27 @@ return "mov{q}\t{%1, %0|%0, %1}"; } } - [(set (attr "type") - (cond [(eq_attr "alternative" "4") + [(set (attr "isa") + (cond [(eq_attr "alternative" "0,1,8") + (const_string "nox64") + (eq_attr "alternative" "2,3,4,5,9,10,11,16,17") + (const_string "x64") + (eq_attr "alternative" "18,19") + (const_string "sse2") + ] + (const_string "*"))) + (set (attr "type") + (cond [(eq_attr "alternative" "0,1") + (const_string "multi") + (eq_attr "alternative" "6") (const_string "mmx") - (eq_attr "alternative" "5,6,7,8") + (eq_attr "alternative" "7,8,9,10,11") (const_string "mmxmov") - (eq_attr "alternative" "9") + (eq_attr "alternative" "12") (const_string "sselog1") - (eq_attr "alternative" "10,11,12,13,14") + (eq_attr "alternative" "13,14,15,16,17") (const_string "ssemov") - (eq_attr "alternative" "15,16") + (eq_attr "alternative" "18,19") (const_string "ssecvt") (match_operand 1 "pic_32bit_operand") (const_string "lea") @@ -1941,159 +1947,43 @@ (const_string "imov"))) (set (attr "modrm") (if_then_else - (and (eq_attr "alternative" "2") (eq_attr "type" "imov")) + (and (eq_attr "alternative" "4") (eq_attr "type" "imov")) (const_string "0") (const_string "*"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "alternative" "2") (eq_attr "type" "imov")) + (and (eq_attr "alternative" "4") (eq_attr "type" "imov")) (const_string "8") (const_string "*"))) (set (attr "prefix_rex") - (if_then_else (eq_attr "alternative" "7,8") + (if_then_else (eq_attr "alternative" "10,11") (const_string "1") (const_string "*"))) + (set (attr "prefix") + (if_then_else (eq_attr "type" "sselog1,ssemov") + (const_string "maybe_vex") + (const_string "orig"))) (set (attr "prefix_data16") - (if_then_else (eq_attr "alternative" "10") + (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI")) (const_string "1") (const_string "*"))) - (set (attr "prefix") - (if_then_else (eq_attr "alternative" "9,10,11,12,13,14") - (const_string "maybe_vex") - (const_string "orig"))) (set (attr "mode") - (cond [(eq_attr "alternative" "0") - (const_string "SI") - (eq_attr "alternative" "9,11") - (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") - (const_string "V4SF") - (match_test "TARGET_AVX") - (const_string "TI") - (match_test "optimize_function_for_size_p (cfun)") - (const_string "V4SF") - ] - (const_string "TI")) - ] - (const_string "DI")))]) + (cond [(eq_attr "alternative" "2") + (const_string "SI") + (eq_attr "alternative" "12,14") + (cond [(ior (not (match_test "TARGET_SSE2")) + (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "TI") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "TI")) -;; Reload patterns to support multi-word load/store -;; with non-offsetable address. -(define_expand "reload_noff_store" - [(parallel [(match_operand 0 "memory_operand" "=m") - (match_operand 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "=&r")])] - "TARGET_64BIT" -{ - rtx mem = operands[0]; - rtx addr = XEXP (mem, 0); - - emit_move_insn (operands[2], addr); - mem = replace_equiv_address_nv (mem, operands[2]); - - emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1])); - DONE; -}) - -(define_expand "reload_noff_load" - [(parallel [(match_operand 0 "register_operand" "=r") - (match_operand 1 "memory_operand" "m") - (match_operand:DI 2 "register_operand" "=r")])] - "TARGET_64BIT" -{ - rtx mem = operands[1]; - rtx addr = XEXP (mem, 0); - - emit_move_insn (operands[2], addr); - mem = replace_equiv_address_nv (mem, operands[2]); - - emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem)); - DONE; -}) - -(define_insn "*movdi_internal" - [(set (match_operand:DI 0 "nonimmediate_operand" - "=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym") - (match_operand:DI 1 "general_operand" - "riFo,riF,C ,*y ,m ,C ,*x,*x,m ,C ,*x,*x,m ,*Ym,*x"))] - "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" -{ - switch (get_attr_type (insn)) - { - case TYPE_SSECVT: - if (SSE_REG_P (operands[0])) - return "movq2dq\t{%1, %0|%0, %1}"; - else - return "movdq2q\t{%1, %0|%0, %1}"; - - case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_TI: - return "%vmovdqa\t{%1, %0|%0, %1}"; - case MODE_DI: - return "%vmovq\t{%1, %0|%0, %1}"; - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - case MODE_V2SF: - return "movlps\t{%1, %0|%0, %1}"; - default: - gcc_unreachable (); - } - - case TYPE_MMXMOV: - return "movq\t{%1, %0|%0, %1}"; - - case TYPE_SSELOG1: - return standard_sse_constant_opcode (insn, operands[1]); - - case TYPE_MMX: - return "pxor\t%0, %0"; - - case TYPE_MULTI: - return "#"; - - default: - gcc_unreachable (); - } -} - [(set (attr "isa") - (cond [(eq_attr "alternative" "5,6,7,8,13,14") - (const_string "sse2") - (eq_attr "alternative" "9,10,11,12") - (const_string "noavx") - ] - (const_string "*"))) - (set (attr "type") - (cond [(eq_attr "alternative" "0,1") - (const_string "multi") - (eq_attr "alternative" "2") - (const_string "mmx") - (eq_attr "alternative" "3,4") - (const_string "mmxmov") - (eq_attr "alternative" "5,9") - (const_string "sselog1") - (eq_attr "alternative" "13,14") - (const_string "ssecvt") - ] - (const_string "ssemov"))) - (set (attr "prefix") - (if_then_else (eq_attr "alternative" "5,6,7,8") - (const_string "maybe_vex") - (const_string "orig"))) - (set (attr "mode") - (cond [(eq_attr "alternative" "9,11") - (const_string "V4SF") - (eq_attr "alternative" "10,12") - (const_string "V2SF") - (eq_attr "alternative" "5,7") - (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") - (const_string "V4SF") - (match_test "TARGET_AVX") - (const_string "TI") - (match_test "optimize_function_for_size_p (cfun)") - (const_string "V4SF") - ] - (const_string "TI")) + (and (eq_attr "alternative" "13,15") + (not (match_test "TARGET_SSE2"))) + (const_string "V2SF") ] (const_string "DI")))]) @@ -2186,6 +2076,7 @@ (const_string "V4SF") ] (const_string "TI")) + (and (eq_attr "alternative" "8,9,10,11") (not (match_test "TARGET_SSE2"))) (const_string "SF") @@ -2896,7 +2787,8 @@ case MODE_V1DF: return "%vmovlpd\t{%1, %d0|%d0, %1}"; case MODE_V2SF: - return "%vmovlps\t{%1, %d0|%d0, %1}"; + gcc_assert (!TARGET_AVX); + return "movlps\t{%1, %0|%0, %1}"; default: gcc_unreachable (); } @@ -2994,10 +2886,9 @@ ] (const_string "DF")) - (eq_attr "alternative" "12,16") - (if_then_else (match_test "TARGET_SSE2") - (const_string "DF") - (const_string "V2SF")) + (and (eq_attr "alternative" "12,16") + (not (match_test "TARGET_SSE2"))) + (const_string "V2SF") ] (const_string "DF")))])