[i386] : Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL in SSE bitops

Message ID	CAFULd4Zn2d+5TF8+MgzDBSEmjOfACHaD+uC8Z9L64UDGr-0o_g@mail.gmail.com
State	New
Headers	show Return-Path: <gcc-patches-return-318737-incoming=patchwork.ozlabs.org@gcc.gnu.org> Comment: DKIM? See http://www.dkim.org Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:MIME-Version:Received:Received:Date:Message-ID:Subject:From:To:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=t/PBD0i4IM3fcLPenWXgo9XEtPYfue32CGkY8TN+bIcZK8BX6oFWasg17Ch6Dd Z4BMqWAVAgdqo9l6Cpda6EA4ikqHLKjN5JIGgLNYHVHLptDOKF5P+CSvpVj7QQXV jDdZke2xN9x8eDHkNou7ErxlwpIW8zsWN0rN+/OO5U/QI=; MIME-Version: 1.0 Date: Sun, 13 May 2012 17:16:43 +0200 Message-ID: <CAFULd4Zn2d+5TF8+MgzDBSEmjOfACHaD+uC8Z9L64UDGr-0o_g@mail.gmail.com> Subject: [PATCH, i386]: Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL in SSE bitops From: Uros Bizjak <ubizjak@gmail.com> To: gcc-patches@gcc.gnu.org Content-Type: multipart/mixed; boundary=20cf303bfad405360204bfec75c8 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 187435) +++ config/i386/sse.md (working copy) @@ -1600,29 +1600,46 @@ "TARGET_SSE" { static char buf[32]; - const char *insn; - const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>"; + const char *ops; + const char *suffix; + switch (get_attr_mode (insn)) + { + case MODE_V8SF: + case MODE_V4SF: + suffix = "ps"; + break; + default: + suffix = "<ssemodesuffix>"; + } + switch (which_alternative) { case 0: - insn = "andn%s\t{%%2, %%0|%%0, %%2}"; + ops = "andn%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "<MODE>")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "<ssePSmode>") + (match_test "TARGET_AVX") + (const_string "<MODE>") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "<MODE>")))]) (define_expand "<code><mode>3" [(set (match_operand:VF 0 "register_operand") @@ -1640,29 +1657,46 @@ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { static char buf[32]; - const char *insn; - const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>"; + const char *ops; + const char *suffix; + switch (get_attr_mode (insn)) + { + case MODE_V8SF: + case MODE_V4SF: + suffix = "ps"; + break; + default: + suffix = "<ssemodesuffix>"; + } + switch (which_alternative) { case 0: - insn = "<logic>%s\t{%%2, %%0|%%0, %%2}"; + ops = "<logic>%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "<MODE>")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "<ssePSmode>") + (match_test "TARGET_AVX") + (const_string "<MODE>") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "<MODE>")))]) (define_expand "copysign<mode>3" [(set (match_dup 4) @@ -1696,30 +1730,85 @@ "SSE_FLOAT_MODE_P (<MODE>mode)" { static char buf[32]; - const char *insn; + const char *ops; const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssevecmodesuffix>"; + = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>"; switch (which_alternative) { case 0: - insn = "andn%s\t{%%2, %%0|%%0, %%2}"; + ops = "andn%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "<ssevecmode>")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "<ssevecmode>") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "<ssevecmode>")))]) +(define_insn "*andnottf3" + [(set (match_operand:TF 0 "register_operand" "=x,x") + (and:TF + (not:TF (match_operand:TF 1 "register_operand" "0,x")) + (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + "TARGET_SSE" +{ + static char buf[32]; + const char *ops; + const char *tmp + = (get_attr_mode (insn) == MODE_V4SF) ? "andnps" : "pandn"; + + switch (which_alternative) + { + case 0: + ops = "%s\t{%%2, %%0|%%0, %%2}"; + break; + case 1: + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + gcc_unreachable (); + } + + snprintf (buf, sizeof (buf), ops, tmp); + return buf; +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set (attr "prefix_data16") + (if_then_else + (and (eq_attr "alternative" "0") + (eq_attr "mode" "TI")) + (const_string "1") + (const_string "*"))) + (set_attr "prefix" "orig,vex") + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "TI") + (ior (not (match_test "TARGET_SSE2")) + (match_test "optimize_function_for_size_p (cfun)")) + (const_string "V4SF") + ] + (const_string "TI")))]) + (define_insn "*<code><mode>3" [(set (match_operand:MODEF 0 "register_operand" "=x,x") (any_logic:MODEF @@ -1728,30 +1817,94 @@ "SSE_FLOAT_MODE_P (<MODE>mode)" { static char buf[32]; - const char *insn; + const char *ops; const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssevecmodesuffix>"; + = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>"; switch (which_alternative) { case 0: - insn = "<logic>%s\t{%%2, %%0|%%0, %%2}"; + ops = "<logic>%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "<ssevecmode>")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "<ssevecmode>") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "<ssevecmode>")))]) +(define_expand "<code>tf3" + [(set (match_operand:TF 0 "register_operand") + (any_logic:TF + (match_operand:TF 1 "nonimmediate_operand") + (match_operand:TF 2 "nonimmediate_operand")))] + "TARGET_SSE" + "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);") + +(define_insn "*<code>tf3" + [(set (match_operand:TF 0 "register_operand" "=x,x") + (any_logic:TF + (match_operand:TF 1 "nonimmediate_operand" "%0,x") + (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + "TARGET_SSE + && ix86_binary_operator_ok (<CODE>, TFmode, operands)" +{ + static char buf[32]; + const char *ops; + const char *tmp + = (get_attr_mode (insn) == MODE_V4SF) ? "<logic>ps" : "p<logic>"; + + switch (which_alternative) + { + case 0: + ops = "%s\t{%%2, %%0|%%0, %%2}"; + break; + case 1: + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + gcc_unreachable (); + } + + snprintf (buf, sizeof (buf), ops, tmp); + return buf; +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set (attr "prefix_data16") + (if_then_else + (and (eq_attr "alternative" "0") + (eq_attr "mode" "TI")) + (const_string "1") + (const_string "*"))) + (set_attr "prefix" "orig,vex") + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "TI") + (ior (not (match_test "TARGET_SSE2")) + (match_test "optimize_function_for_size_p (cfun)")) + (const_string "V4SF") + ] + (const_string "TI")))]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; FMA4 floating point multiply/accumulate instructions. This @@ -6659,45 +6812,6 @@ ] (const_string "<sseinsnmode>")))]) -(define_insn "*andnottf3" - [(set (match_operand:TF 0 "register_operand" "=x,x") - (and:TF - (not:TF (match_operand:TF 1 "register_operand" "0,x")) - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] - "TARGET_SSE2" - "@ - pandn\t{%2, %0|%0, %2} - vpandn\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "sselog") - (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "TI")]) - -(define_expand "<code>tf3" - [(set (match_operand:TF 0 "register_operand") - (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand") - (match_operand:TF 2 "nonimmediate_operand")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);") - -(define_insn "*<code>tf3" - [(set (match_operand:TF 0 "register_operand" "=x,x") - (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand" "%0,x") - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] - "TARGET_SSE2 - && ix86_binary_operator_ok (<CODE>, TFmode, operands)" - "@ - p<logic>\t{%2, %0|%0, %2} - vp<logic>\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "sselog") - (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "TI")]) - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral element swizzling

[i386] : Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL in SSE bitops

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