From patchwork Wed Jan 31 19:47:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 868050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-472414-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="dfnpqoS0"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zWv0R2y1rz9sP9 for ; Thu, 1 Feb 2018 06:47:19 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=XQEOpto4vNFbPOHCyIRITgj5rdy50vw6Cy2C37zFstL EyVZuWdPQ8QjkJgQqUxggadKQOgI7KmpD69TXFRHmWfT0n30EYfqcYmndVbj3/S3 j0Fm54IjhiDLGIqtYi2Upi/OVQQOqPfvM0ze+ex0OMVPNrCye/ifn/ug2dgtb+6w = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=N1I1JXfefSbJGyJvW/H6orktmtA=; b=dfnpqoS0fzPD8LhMH zXvnncOOAWwcIfSRf4mCN2NpyGVTA8ulELXH/7lokawWliJTi9w8yABieBxQC0pw 3mKIvpXv34hNp68b1aUWT5/Oxmt2/tF+OCN7bi7Fjht9yJsHLGJ5ShnG01tYlsfD cBN7ucz/NSHjRTl7G03ehNg6lA= Received: (qmail 123722 invoked by alias); 31 Jan 2018 19:47:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 123711 invoked by uid 89); 31 Jan 2018 19:47:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=hello! X-HELO: mail-io0-f170.google.com Received: from mail-io0-f170.google.com (HELO mail-io0-f170.google.com) (209.85.223.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 31 Jan 2018 19:47:10 +0000 Received: by mail-io0-f170.google.com with SMTP id p188so16468497ioe.12 for ; Wed, 31 Jan 2018 11:47:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=SaGAUIDjx7Swr/hIhA91WjEVEy3s2ie+OgbHhPx2gFs=; b=GctwFDM0jQytETZryHPbOAE4HHO30fJ/ej/d4wxskDoj28Dujbo00PykJB8/uOguCk Ed4R6bHpnL23flUS5sVoJmwklDFHvsL2WjcwSFrZeUR7dQAZVI08yKPc1HF3yCPsBxk1 g91dGy8Idyv8ghoD8z6RJdkxxd81KsLusBxsN15zuaVul1kSTHUtTtBe1+Ie0ekJNzMS gvM+rgLMtZLZSlLr8s/R9FnTOJKuiDFTYOjEvuhrHU5mmYX51MUF5aEJ23wfO+WtS8UE yTBbUk+saU6nj+0M47slbVm6zT5lEXlbO73ZIC5xkjiHo7cEirOMJUU+dKvCI5UIqMZs /cWA== X-Gm-Message-State: AKwxytdSGarmdl0Ue7Kof1f0sFDsC8RIRDvWUiP15PeI6fKCFpGojSRo A4zlAL00euVESilL4MRamoU0CeTwIZXDHaKgwHOatA== X-Google-Smtp-Source: AH8x224rxD8RjNTlWuIfa++Jy+bNZmo0/BBjE66x1qBsus4/x5PrIDzi6JABB8njCQpE436azIHFuk+g7WQnNFW/pJI= X-Received: by 10.107.180.146 with SMTP id d140mr37796363iof.166.1517428028596; Wed, 31 Jan 2018 11:47:08 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.181.171 with HTTP; Wed, 31 Jan 2018 11:47:08 -0800 (PST) From: Uros Bizjak Date: Wed, 31 Jan 2018 20:47:08 +0100 Message-ID: Subject: [PATCH, combine]: Fix PR84123: internal compiler error: in gen_rtx_SUBREG, at emit-rtl.c To: "gcc-patches@gcc.gnu.org" Cc: Segher Boessenkool Hello! As shown in the PR, alpha specific testcase hits the above ICE when combine pass is trying to simplify: (insn 13 12 16 2 (set (reg:SI 141 [ ID ]) (zero_extend:SI (subreg:QI (reg:DI 48 $f16 [ ID ]) 0))) 48 {zero_extendqisi2} via change_zero_ext (combine.c): 11486 else if (GET_CODE (x) == ZERO_EXTEND 11487 && GET_CODE (XEXP (x, 0)) == SUBREG 11488 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0)))) 11489 && !paradoxical_subreg_p (XEXP (x, 0)) 11490 && subreg_lowpart_p (XEXP (x, 0))) 11491 { 11492 inner_mode = as_a (GET_MODE (XEXP (x, 0))); 11493 size = GET_MODE_PRECISION (inner_mode); 11494 x = SUBREG_REG (XEXP (x, 0)); 11495 if (GET_MODE (x) != mode) 11496 x = gen_lowpart_SUBREG (mode, x); 11497 } This won't work when x in line 11496 is a hard register and mode is unsupported with targetm.hard_regno_mode_ok. (gdb) p debug_rtx (x) (reg:DI 48 $f16 [ ID ]) $1 = void (gdb) p mode $2 = {m_mode = E_SImode} (which in case of alpha is defined as: --cut here-- /* Implement TARGET_HARD_REGNO_MODE_OK. On Alpha, the integer registers can hold any mode. The floating-point registers can hold 64-bit integers as well, but not smaller values. */ static bool alpha_hard_regno_mode_ok (unsigned int regno, machine_mode mode) { if (IN_RANGE (regno, 32, 62)) return (mode == SFmode || mode == DFmode || mode == DImode || mode == SCmode || mode == DCmode); return true; } --cut here-- We should skip RTXes that will result in certain ICE here, and this is what the attached patch does. 2018-01-31 Uros Bizjak PR target/84123 * combine.c (change_zero_ext): Check if hard register satisfies can_change_dest_mode before calling gen_lowpart_SUBREG. Patch was bootstrapped and regression tested on alphaev68-linux-gnu (native bootstrap) and x86_64-linux-gnu {,-m32}. OK for mainline and backports? Uros. diff --git a/gcc/combine.c b/gcc/combine.c index 6adc0a7d6f8..c59c2156fa1 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -11480,8 +11480,15 @@ change_zero_ext (rtx pat) gen_int_shift_amount (inner_mode, start)); else x = XEXP (x, 0); + if (mode != inner_mode) - x = gen_lowpart_SUBREG (mode, x); + { + if (HARD_REGISTER_P (x) + && !can_change_dest_mode (x, 0, mode)) + continue; + + x = gen_lowpart_SUBREG (mode, x); + } } else if (GET_CODE (x) == ZERO_EXTEND && GET_CODE (XEXP (x, 0)) == SUBREG @@ -11493,7 +11500,13 @@ change_zero_ext (rtx pat) size = GET_MODE_PRECISION (inner_mode); x = SUBREG_REG (XEXP (x, 0)); if (GET_MODE (x) != mode) - x = gen_lowpart_SUBREG (mode, x); + { + if (HARD_REGISTER_P (x) + && !can_change_dest_mode (x, 0, mode)) + continue; + + x = gen_lowpart_SUBREG (mode, x); + } } else if (GET_CODE (x) == ZERO_EXTEND && REG_P (XEXP (x, 0))