diff mbox series

[committed] i386: Do not use commutative operands with (use) RTX [PR95238]

Message ID CAFULd4ZRyMDGyZxA2d_hejxcVR5G30V-T+1Jf8LN0Ro_0dQfQA@mail.gmail.com
State New
Headers show
Series [committed] i386: Do not use commutative operands with (use) RTX [PR95238] | expand

Commit Message

Uros Bizjak May 20, 2020, 11:56 p.m. UTC 
2020-05-21  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:
    PR target/95218

    * config/i386/mmx.md (*mmx_<code>v2sf): Do not mark
    operands 1 and 2 commutative.  Manually swap operands.
    (*mmx_nabsv2sf2): Ditto.

    Partially revert:
    2020-05-18  Uroš Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md (*<code>tf2_1):
    Mark operands 1 and 2 commutative.
    (*nabstf2_1): Ditto.
    * config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
    commutative.  Do not swap operands.
    (*nabs<mode>2): Ditto.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 29c2b4795f0..e81c737b7bc 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10037,31 +10037,53 @@ 
   "ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
 
 (define_insn_and_split "*<code>tf2_1"
-  [(set (match_operand:TF 0 "register_operand" "=x,Yv")
+  [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv")
 	(absneg:TF
-	  (match_operand:TF 1 "vector_operand" "%0,Yv")))
-   (use (match_operand:TF 2 "vector_operand" "xBm,Yvm"))]
+	  (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m")))
+   (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv"))]
   "TARGET_SSE"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(<absneg_op>:TF (match_dup 1) (match_dup 2)))]
-  ""
-  [(set_attr "isa" "noavx,avx")])
+{
+  if (TARGET_AVX)
+    {
+      if (MEM_P (operands[1]))
+        std::swap (operands[1], operands[2]);
+    }
+  else
+   {
+     if (operands_match_p (operands[0], operands[2]))
+       std::swap (operands[1], operands[2]);
+   }
+}
+  [(set_attr "isa" "noavx,noavx,avx,avx")])
 
 (define_insn_and_split "*nabstf2_1"
-  [(set (match_operand:TF 0 "register_operand" "=x,Yv")
+  [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv")
 	(neg:TF
 	  (abs:TF
-	    (match_operand:TF 1 "vector_operand" "%0,Yv"))))
-   (use (match_operand:TF 2 "vector_operand" "xBm,Yvm"))]
+	    (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m"))))
+   (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv"))]
   "TARGET_SSE"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(ior:TF (match_dup 1) (match_dup 2)))]
-  ""
-  [(set_attr "isa" "noavx,avx")])
+{
+  if (TARGET_AVX)
+    {
+      if (MEM_P (operands[1]))
+        std::swap (operands[1], operands[2]);
+    }
+  else
+   {
+     if (operands_match_p (operands[0], operands[2]))
+       std::swap (operands[1], operands[2]);
+   }
+}
+  [(set_attr "isa" "noavx,noavx,avx,avx")])
 
 (define_expand "<code><mode>2"
   [(set (match_operand:X87MODEF 0 "register_operand")
@@ -10117,7 +10139,7 @@ 
 (define_split
   [(set (match_operand:MODEF 0 "sse_reg_operand")
 	(absneg:MODEF
-	  (match_operand:MODEF 1 "vector_operand")))
+	  (match_operand:MODEF 1 "sse_reg_operand")))
    (use (match_operand:<ssevecmodef> 2 "vector_operand"))
    (clobber (reg:CC FLAGS_REG))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
@@ -10152,7 +10174,7 @@ 
   [(const_int 0)]
   "ix86_split_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
 
-(define_insn "*nabs<mode>2_1"
+(define_insn_and_split "*nabs<mode>2_1"
   [(set (match_operand:MODEF 0 "register_operand" "=x,x,Yv")
 	(neg:MODEF
 	  (abs:MODEF
@@ -10160,16 +10182,7 @@ 
    (use (match_operand:<ssevecmode> 2 "vector_operand" "xBm,0,Yvm"))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "#"
-  [(set_attr "isa" "noavx,noavx,avx")])
-
-(define_split
-  [(set (match_operand:MODEF 0 "sse_reg_operand")
-	(neg:MODEF
-	  (abs:MODEF
-	    (match_operand:MODEF 1 "vector_operand"))))
-   (use (match_operand:<ssevecmodef> 2 "vector_operand"))]
-  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
-   && reload_completed"
+  "&& reload_completed"
   [(set (match_dup 0)
 	(ior:<ssevecmodef> (match_dup 1) (match_dup 2)))]
 {
@@ -10181,7 +10194,8 @@ 
 
   if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
     std::swap (operands[1], operands[2]);
-})
+}
+  [(set_attr "isa" "noavx,noavx,avx")])
 
 ;; Conditionalize these after reload. If they match before reload, we
 ;; lose the clobber and ability to use integer instructions.
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index f73c8452651..5deef683b0b 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -246,31 +246,37 @@ 
   "ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
 
 (define_insn_and_split "*mmx_<code>v2sf2"
-  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
 	(absneg:V2SF
-	  (match_operand:V2SF 1 "register_operand" "%0,x")))
-   (use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
+	  (match_operand:V2SF 1 "register_operand" "0,x,x")))
+   (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
   "TARGET_MMX_WITH_SSE"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
-  ""
-  [(set_attr "isa" "noavx,avx")])
+{
+  if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
+    std::swap (operands[1], operands[2]);
+}
+  [(set_attr "isa" "noavx,noavx,avx")])
 
 (define_insn_and_split "*mmx_nabsv2sf2"
-  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
 	(neg:V2SF
 	  (abs:V2SF
-	    (match_operand:V2SF 1 "register_operand" "%0,x"))))
-   (use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
+	    (match_operand:V2SF 1 "register_operand" "0,x,x"))))
+   (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
   "TARGET_MMX_WITH_SSE"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(ior:V2SF (match_dup 1) (match_dup 2)))]
-  ""
-  [(set_attr "isa" "noavx,avx")])
+{
+  if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
+    std::swap (operands[1], operands[2]);
+}
+  [(set_attr "isa" "noavx,noavx,avx")])
 
 (define_expand "mmx_addv2sf3"
   [(set (match_operand:V2SF 0 "register_operand")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c831543b4e9..5071fb2895a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1638,31 +1638,53 @@ 
   "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
 
 (define_insn_and_split "*<code><mode>2"
-  [(set (match_operand:VF 0 "register_operand" "=x,v")
+  [(set (match_operand:VF 0 "register_operand" "=x,x,v,v")
 	(absneg:VF
-	  (match_operand:VF 1 "vector_operand" "%0,v")))
-   (use (match_operand:VF 2 "vector_operand" "xBm,vm"))]
+	  (match_operand:VF 1 "vector_operand" "0,xBm,v,m")))
+   (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))]
   "TARGET_SSE"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(<absneg_op>:VF (match_dup 1) (match_dup 2)))]
-  ""
-  [(set_attr "isa" "noavx,avx")])
+{
+  if (TARGET_AVX)
+    {
+      if (MEM_P (operands[1]))
+        std::swap (operands[1], operands[2]);
+    }
+  else
+   {
+     if (operands_match_p (operands[0], operands[2]))
+       std::swap (operands[1], operands[2]);
+   }
+}
+  [(set_attr "isa" "noavx,noavx,avx,avx")])
 
 (define_insn_and_split "*nabs<mode>2"
-  [(set (match_operand:VF 0 "register_operand" "=x,v")
+  [(set (match_operand:VF 0 "register_operand" "=x,x,v,v")
 	(neg:VF
 	  (abs:VF
-	    (match_operand:VF 1 "vector_operand" "%0,v"))))
-   (use (match_operand:VF 2 "vector_operand" "xBm,vm"))]
+	    (match_operand:VF 1 "vector_operand" "0,xBm,v,m"))))
+   (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))]
   "TARGET_SSE"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(ior:VF (match_dup 1) (match_dup 2)))]
-  ""
-  [(set_attr "isa" "noavx,avx")])
+{
+  if (TARGET_AVX)
+    {
+      if (MEM_P (operands[1]))
+        std::swap (operands[1], operands[2]);
+    }
+  else
+   {
+     if (operands_match_p (operands[0], operands[2]))
+       std::swap (operands[1], operands[2]);
+   }
+}
+  [(set_attr "isa" "noavx,noavx,avx,avx")])
 
 (define_expand "<plusminus_insn><mode>3<mask_name><round_name>"
   [(set (match_operand:VF 0 "register_operand")