diff mbox series

[RFC] i386: Add V2SFmode FMA insn patterns [PR95046]

Message ID CAFULd4ZAA3knCzi4ELfMoZA1WL+MKVFVNy_NBLQjSVnO4kv_2w@mail.gmail.com
State New
Headers show
Series [RFC] i386: Add V2SFmode FMA insn patterns [PR95046] | expand

Commit Message

Uros Bizjak May 11, 2020, 7:52 p.m. UTC 
Attached patch implements V2SFmode FMA insn patterns. Patched compiler
vectorizes FMA, FMS and FNMA instructions, but for some reason fails
to vectorize FNMS.

I have double checked that the insn pattern is correct, and now I'm
all out of ideas what could be wrong with the pattern, still ignored
by the vectorizer. -fno-vect-cost-model does not help so it's time to
ask the experts...

gcc/ChangeLog:

2020-05-11  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * config/i386/mmx.md (fmav2sf4): New insn pattern.
    (fmsv2sf4): Ditto.
    (fnmav2sf4): Ditto.
    (fnmsv2sf4): Ditto.

testsuite/ChangeLog:

2020-05-11  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * gcc.target/i386/pr95046-2.c: New test.

Otherwise, the patch is bootstrapped and regression tested on
x86_64-linux-gnu {,-m32}.

Uros.

Comments

Richard Biener May 12, 2020, 5:56 a.m. UTC | #1 
On Mon, 11 May 2020, Uros Bizjak wrote:

> Attached patch implements V2SFmode FMA insn patterns. Patched compiler
> vectorizes FMA, FMS and FNMA instructions, but for some reason fails
> to vectorize FNMS.
> 
> I have double checked that the insn pattern is correct, and now I'm
> all out of ideas what could be wrong with the pattern, still ignored
> by the vectorizer. -fno-vect-cost-model does not help so it's time to
> ask the experts...

Do you have negate patterns for V2SFmode?  The vectorizer sees
decomposed ops and only the vectorized operations are later formed
into FMAs.

Richard.

> gcc/ChangeLog:
> 
> 2020-05-11  Uroš Bizjak  <ubizjak@gmail.com>
> 
>     PR target/95046
>     * config/i386/mmx.md (fmav2sf4): New insn pattern.
>     (fmsv2sf4): Ditto.
>     (fnmav2sf4): Ditto.
>     (fnmsv2sf4): Ditto.
> 
> testsuite/ChangeLog:
> 
> 2020-05-11  Uroš Bizjak  <ubizjak@gmail.com>
> 
>     PR target/95046
>     * gcc.target/i386/pr95046-2.c: New test.
> 
> Otherwise, the patch is bootstrapped and regression tested on
> x86_64-linux-gnu {,-m32}.
> 
> Uros.
>
Uros Bizjak May 12, 2020, 6:17 a.m. UTC | #2 
On Tue, May 12, 2020 at 7:57 AM Richard Biener <rguenther@suse.de> wrote:
>
> On Mon, 11 May 2020, Uros Bizjak wrote:
>
> > Attached patch implements V2SFmode FMA insn patterns. Patched compiler
> > vectorizes FMA, FMS and FNMA instructions, but for some reason fails
> > to vectorize FNMS.
> >
> > I have double checked that the insn pattern is correct, and now I'm
> > all out of ideas what could be wrong with the pattern, still ignored
> > by the vectorizer. -fno-vect-cost-model does not help so it's time to
> > ask the experts...
>
> Do you have negate patterns for V2SFmode?  The vectorizer sees
> decomposed ops and only the vectorized operations are later formed
> into FMAs.

No, not yet.

I'll add V2SF absneg next; they require some surgery in
ix86_expand_fp_absneg_operator, so I left them for "later.

Thanks,
Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index a8f603b94f8..0024ce761d7 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -345,6 +345,70 @@ 
    (set_attr "prefix" "*,orig,vex")
    (set_attr "mode" "V2SF,V4SF,V4SF")])
 
+(define_insn "fmav2sf4"
+  [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+	(fma:V2SF
+	  (match_operand:V2SF 1 "register_operand" "%0,v,x")
+	  (match_operand:V2SF 2 "register_operand" "v,v,x")
+	  (match_operand:V2SF 3 "register_operand" "v,0,x")))]
+  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "@
+   vfmadd132ps\t{%2, %3, %0|%0, %3, %2}
+   vfmadd231ps\t{%2, %1, %0|%0, %1, %2}
+   vfmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma4")
+   (set_attr "type" "ssemuladd")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "fmsv2sf4"
+  [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+	(fma:V2SF
+	  (match_operand:V2SF   1 "register_operand" "%0,v,x")
+	  (match_operand:V2SF   2 "register_operand" "v,v,x")
+	  (neg:V2SF
+	    (match_operand:V2SF 3 "register_operand" "v,0,x"))))]
+  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "@
+   vfmsub132ps\t{%2, %3, %0|%0, %3, %2}
+   vfmsub231ps\t{%2, %1, %0|%0, %1, %2}
+   vfmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma4")
+   (set_attr "type" "ssemuladd")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "fnmav2sf4"
+  [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+	(fma:V2SF
+	  (neg:V2SF
+	    (match_operand:V2SF 1 "register_operand" "%0,v,x"))
+	  (match_operand:V2SF   2 "register_operand" "v,v,x")
+	  (match_operand:V2SF   3 "register_operand" "v,0,x")))]
+  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "@
+   vfnmadd132ps\t{%2, %3, %0|%0, %3, %2}
+   vfnmadd231ps\t{%2, %1, %0|%0, %1, %2}
+   vfnmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma4")
+   (set_attr "type" "ssemuladd")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "fnmsv2sf4"
+  [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+	(fma:V2SF
+	  (neg:V2SF
+	    (match_operand:V2SF 1 "register_operand" "%0,v,x"))
+	  (match_operand:V2SF   2 "register_operand" "v,v,x")
+	  (neg:V2SF
+	    (match_operand:V2SF 3 "register_operand" "v,0,x"))))]
+  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "@
+   vfnmsub132ps\t{%2, %3, %0|%0, %3, %2}
+   vfnmsub231ps\t{%2, %1, %0|%0, %1, %2}
+   vfnmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "fma,fma,fma4")
+   (set_attr "type" "ssemuladd")
+   (set_attr "mode" "V4SF")])
+
 (define_expand "mmx_<code>v2sf3"
   [(set (match_operand:V2SF 0 "register_operand")
         (smaxmin:V2SF