From patchwork Thu Jan 12 17:32:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 714562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tztBK0YmTz9tld for ; Fri, 13 Jan 2017 04:32:40 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ob3DBXOS"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=bQGFF1yOy3+N5KptyXcokJp01hHy/wa5NcBxIfGTNX+8y5 VU36RW4BLk0UIoQXbS0qZvC8So6vICE3zJ/DBYcyaGCsYhswHXc1InF15wQktJPC JSjgyNQMh2VNj7hv142AHU2eOvvKDqIt0IrtkAoyl35El1kdV9ahpOPq2C72k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=1Z/mVWuNe6VPJebt9HA2wKKX94M=; b=ob3DBXOS6ZD7YcvAi0KF MBM17sky/gBTIGMcGR9uNioa3WW09diKNQVeFAOUXNxmTq2vb3NIx9O8UJFbe3r3 QK8T9kGAOq/ZHW7sSlixBagIwm6yH8ZfWLjfZCULwkL/TCHnsSZGCNDdrh8ivp2A bCk+UArVmqxu6wPnA06udwY= Received: (qmail 86179 invoked by alias); 12 Jan 2017 17:32:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 86148 invoked by uid 89); 12 Jan 2017 17:32:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.6 required=5.0 tests=AWL, BAYES_05, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=Extended, fma4, avx512er, bmi X-HELO: mail-ua0-f179.google.com Received: from mail-ua0-f179.google.com (HELO mail-ua0-f179.google.com) (209.85.217.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 12 Jan 2017 17:32:24 +0000 Received: by mail-ua0-f179.google.com with SMTP id 96so19241520uaq.3 for ; Thu, 12 Jan 2017 09:32:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=v15mzGvMwpMbXIJQXBmrlRkx9hGnWDQvKwQqCMw6aaA=; b=f/gX8D1pARZu6Ef9VkuW1jevXfSSXfikZL0MRpDYN582jHumtJD4HMiLZZRGQRKfY2 53hr2ExBQE8qks/l20uUaPdt1uCbzdc2rMCVzT6F5doPJUUb+raIWGU5vnmGbZRwvVsY aPRknsEJO/ZmxqiFHquDyyg24YLV15KvmFRLI495LsFs2nYVT+J4nY1EDjLlQNEB1JO1 /r7DZaKMZA4MsLz1vQJLoIgslnw2mShrXez9AhAUM5P2+wNGL/M5UCl1Fk52/QOJ+U7X bsUZ6nT4E1U4y8xUJtJNXWlYPpV8q1jugSYzCLG5RFuxz56tHbjmzjZ4jPo/kVP3eD1v oL/w== X-Gm-Message-State: AIkVDXJdpHE+N1ryUX8g7Q01y/FC567x/yD14r47I1Jr0jFf/O4G1BSh1hBNkdD/oqRIvh9iscmrnhNvW4udtw== X-Received: by 10.159.35.52 with SMTP id 49mr8205260uae.113.1484242342935; Thu, 12 Jan 2017 09:32:22 -0800 (PST) MIME-Version: 1.0 Received: by 10.103.87.11 with HTTP; Thu, 12 Jan 2017 09:32:22 -0800 (PST) From: Uros Bizjak Date: Thu, 12 Jan 2017 18:32:22 +0100 Message-ID: Subject: [PATCH, i386 testsuite]: Check all supported __builtin_cpu_supports options To: "gcc-patches@gcc.gnu.org" Hello! Attached patch checks all supported __builtin_cpu_supports options. Additionally, it adds a couple of comments and moves some code to prevent future mistakes. 2017-01-12 Uros Bizjak * gcc.target/i386/builtin_target.c (check_features): Check all supported __builtin_cpu_supports options. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: gcc/config/i386/cpuid.h =================================================================== --- gcc/config/i386/cpuid.h (revision 244369) +++ gcc/config/i386/cpuid.h (working copy) @@ -47,7 +47,7 @@ #define bit_SSE (1 << 25) #define bit_SSE2 (1 << 26) -/* Extended Features */ +/* Extended Features (%eax == 0x80000001) */ /* %ecx */ #define bit_LAHF_LM (1 << 0) #define bit_ABM (1 << 5) @@ -54,7 +54,6 @@ #define bit_SSE4a (1 << 6) #define bit_PRFCHW (1 << 8) #define bit_XOP (1 << 11) -#define bit_AVX512VPOPCNTDQ (1 << 14) #define bit_LWP (1 << 15) #define bit_FMA4 (1 << 16) #define bit_TBM (1 << 21) @@ -61,14 +60,12 @@ #define bit_MWAITX (1 << 29) /* %edx */ -#define bit_AVX5124VNNIW (1 << 2) -#define bit_AVX5124FMAPS (1 << 3) #define bit_MMXEXT (1 << 22) #define bit_LM (1 << 29) #define bit_3DNOWP (1 << 30) #define bit_3DNOW (1 << 31) -/* %ebx. */ +/* %ebx */ #define bit_CLZERO (1 << 0) /* Extended Features (%eax == 7) */ @@ -100,7 +97,12 @@ #define bit_AVX512VBMI (1 << 1) #define bit_PKU (1 << 3) #define bit_OSPKE (1 << 4) +#define bit_AVX512VPOPCNTDQ (1 << 14) +/* %edx */ +#define bit_AVX5124VNNIW (1 << 2) +#define bit_AVX5124FMAPS (1 << 3) + /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ #define bit_BNDREGS (1 << 3) #define bit_BNDCSR (1 << 4) Index: gcc/testsuite/gcc.target/i386/builtin_target.c =================================================================== --- gcc/testsuite/gcc.target/i386/builtin_target.c (revision 244369) +++ gcc/testsuite/gcc.target/i386/builtin_target.c (working copy) @@ -163,6 +163,9 @@ check_features (unsigned int ecx, unsigned int edx, int max_cpuid_level) { + unsigned int eax, ebx; + unsigned int ext_level; + if (edx & bit_CMOV) assert (__builtin_cpu_supports ("cmov")); if (edx & bit_MMX) @@ -187,18 +190,27 @@ assert (__builtin_cpu_supports ("sse4.2")); if (ecx & bit_AVX) assert (__builtin_cpu_supports ("avx")); + if (ecx & bit_FMA) + assert (__builtin_cpu_supports ("fma")); /* Get advanced features at level 7 (eax = 7, ecx = 0). */ if (max_cpuid_level >= 7) { - unsigned int eax, ebx, ecx, edx; __cpuid_count (7, 0, eax, ebx, ecx, edx); + if (ebx & bit_BMI) + assert (__builtin_cpu_supports ("bmi")); if (ebx & bit_AVX2) assert (__builtin_cpu_supports ("avx2")); + if (ebx & bit_BMI2) + assert (__builtin_cpu_supports ("bmi2")); if (ebx & bit_AVX512F) assert (__builtin_cpu_supports ("avx512f")); if (ebx & bit_AVX512VL) assert (__builtin_cpu_supports ("avx512vl")); + if (ebx & bit_AVX512BW) + assert (__builtin_cpu_supports ("avx512bw")); + if (ebx & bit_AVX512DQ) + assert (__builtin_cpu_supports ("avx512dq")); if (ebx & bit_AVX512CD) assert (__builtin_cpu_supports ("avx512cd")); if (ebx & bit_AVX512PF) @@ -205,21 +217,32 @@ assert (__builtin_cpu_supports ("avx512pf")); if (ebx & bit_AVX512ER) assert (__builtin_cpu_supports ("avx512er")); - if (ebx & bit_AVX512BW) - assert (__builtin_cpu_supports ("avx512bw")); - if (ebx & bit_AVX512DQ) - assert (__builtin_cpu_supports ("avx512dq")); - if (ecx & bit_AVX512IFMA) + if (ebx & bit_AVX512IFMA) assert (__builtin_cpu_supports ("avx512ifma")); if (ecx & bit_AVX512VBMI) assert (__builtin_cpu_supports ("avx512vbmi")); + if (ecx & bit_AVX512VPOPCNTDQ) + assert (__builtin_cpu_supports ("avx512vpopcntdq")); if (edx & bit_AVX5124VNNIW) assert (__builtin_cpu_supports ("avx5124vnniw")); if (edx & bit_AVX5124FMAPS) assert (__builtin_cpu_supports ("avx5124fmaps")); - if (ecx & bit_AVX512VPOPCNTDQ) - assert (__builtin_cpu_supports ("avx512vpopcntdq")); } + + /* Check cpuid level of extended features. */ + __cpuid (0x80000000, ext_level, ebx, ecx, edx); + + if (ext_level >= 0x80000001) + { + __cpuid (0x80000001, eax, ebx, ecx, edx); + + if (ecx & bit_SSE4a) + assert (__builtin_cpu_supports ("sse4a")); + if (ecx & bit_FMA4) + assert (__builtin_cpu_supports ("fma4")); + if (ecx & bit_XOP) + assert (__builtin_cpu_supports ("xop")); + } } static int __attribute__ ((noinline)) Index: libgcc/config/i386/cpuinfo.c =================================================================== --- libgcc/config/i386/cpuinfo.c (revision 244369) +++ libgcc/config/i386/cpuinfo.c (working copy) @@ -215,6 +215,9 @@ get_available_features (unsigned int ecx, unsigned int edx, int max_cpuid_level) { + unsigned int eax, ebx; + unsigned int ext_level; + unsigned int features = 0; if (edx & bit_CMOV) @@ -247,7 +250,6 @@ /* Get Advanced Features at level 7 (eax = 7, ecx = 0). */ if (max_cpuid_level >= 7) { - unsigned int eax, ebx, ecx, edx; __cpuid_count (7, 0, eax, ebx, ecx, edx); if (ebx & bit_BMI) features |= (1 << FEATURE_BMI); @@ -273,20 +275,18 @@ features |= (1 << FEATURE_AVX512IFMA); if (ecx & bit_AVX512VBMI) features |= (1 << FEATURE_AVX512VBMI); + if (ecx & bit_AVX512VPOPCNTDQ) + features |= (1 << FEATURE_AVX512VPOPCNTDQ); if (edx & bit_AVX5124VNNIW) features |= (1 << FEATURE_AVX5124VNNIW); if (edx & bit_AVX5124FMAPS) features |= (1 << FEATURE_AVX5124FMAPS); - if (ecx & bit_AVX512VPOPCNTDQ) - features |= (1 << FEATURE_AVX512VPOPCNTDQ); } - unsigned int ext_level; - unsigned int eax, ebx; /* Check cpuid level of extended features. */ __cpuid (0x80000000, ext_level, ebx, ecx, edx); - if (ext_level > 0x80000000) + if (ext_level >= 0x80000001) { __cpuid (0x80000001, eax, ebx, ecx, edx);