From patchwork Sun Nov 20 19:11:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 126660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id EF528B7226 for ; Mon, 21 Nov 2011 06:11:39 +1100 (EST) Received: (qmail 18219 invoked by alias); 20 Nov 2011 19:11:38 -0000 Received: (qmail 18210 invoked by uid 22791); 20 Nov 2011 19:11:37 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-gx0-f175.google.com (HELO mail-gx0-f175.google.com) (209.85.161.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 20 Nov 2011 19:11:24 +0000 Received: by ggnh4 with SMTP id h4so4436066ggn.20 for ; Sun, 20 Nov 2011 11:11:23 -0800 (PST) MIME-Version: 1.0 Received: by 10.236.181.225 with SMTP id l61mr15368253yhm.131.1321816281954; Sun, 20 Nov 2011 11:11:21 -0800 (PST) Received: by 10.146.137.4 with HTTP; Sun, 20 Nov 2011 11:11:21 -0800 (PST) Date: Sun, 20 Nov 2011 20:11:21 +0100 Message-ID: Subject: [PATCH, i386]: Fix ICE in tree-ssa/prefetch-[89].c From: Uros Bizjak To: gcc-patches@gcc.gnu.org Cc: "H.J. Lu" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! Renaming UNSPEC_MOVNT to UNSPEC_MOVNTI was not a good idea, since it caused [1]: prefetch-8.c: In function ‘test’: prefetch-8.c:16:1: error: unrecognizable insn: (insn 15 14 16 4 (set (mem:SI (plus:SI (mult:SI (reg/v:SI 64 [ i ]) (const_int 4 [0x4])) (reg/f:SI 65)) [2 MEM[symbol: a, index: i_9, step: 4, offset: 0B]+0 S4 A32]) (unspec:SI [ (reg:SI 66) ] UNSPEC_MOVNT)) prefetch-8.c:15 -1 (nil)) prefetch-8.c:16:1: internal compiler error: in extract_insn, at recog.c:2137 Fixed by attached patch that also added missing modes to STORENT_MODE mode iterator. 2011-11-20 Uros Bizjak * config/i386/i386.md (UNSPEC_MOVNTI): Remove. (UNSPEC_MOVNTQ): New unspec. * config/i386/mmx.md (sse_movntdi): Use UNSPEC_MOVNTQ instead of UNSPEC_MOVNT. * config/i386/sse.md (sse2_movnti): Use UNSPEC_MOVNT instead of UNSPEC_MOVNTI. (STORENT_MODE): Add DI and V4DI modes. Patch was tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline SVN. [1] http://gcc.gnu.org/ml/gcc-testresults/2011-11/msg02046.html Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 181530) +++ config/i386/i386.md (working copy) @@ -115,8 +115,8 @@ UNSPEC_FIX_NOTRUNC UNSPEC_MASKMOV UNSPEC_MOVMSK + UNSPEC_MOVNTQ UNSPEC_MOVNT - UNSPEC_MOVNTI UNSPEC_MOVU UNSPEC_RCP UNSPEC_RSQRT Index: config/i386/mmx.md =================================================================== --- config/i386/mmx.md (revision 181530) +++ config/i386/mmx.md (working copy) @@ -332,7 +332,7 @@ (define_insn "sse_movntdi" [(set (match_operand:DI 0 "memory_operand" "=m") (unspec:DI [(match_operand:DI 1 "register_operand" "y")] - UNSPEC_MOVNT))] + UNSPEC_MOVNTQ))] "TARGET_SSE || TARGET_3DNOW_A" "movntq\t{%1, %0|%0, %1}" [(set_attr "type" "mmxmov") Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 181530) +++ config/i386/sse.md (working copy) @@ -576,7 +576,7 @@ (define_insn "sse2_movnti" [(set (match_operand:SWI48 0 "memory_operand" "=m") (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")] - UNSPEC_MOVNTI))] + UNSPEC_MOVNT))] "TARGET_SSE2" "movnti\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") @@ -614,8 +614,9 @@ ;; Modes handled by storent patterns. (define_mode_iterator STORENT_MODE - [(SI "TARGET_SSE2") (SF "TARGET_SSE4A") (DF "TARGET_SSE4A") - (V2DI "TARGET_SSE2") + [(DI "TARGET_SSE2 && TARGET_64BIT") (SI "TARGET_SSE2") + (SF "TARGET_SSE4A") (DF "TARGET_SSE4A") + (V4DI "TARGET_AVX") (V2DI "TARGET_SSE2") (V8SF "TARGET_AVX") V4SF (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])