From patchwork Tue May 7 17:54:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 242430 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id C0B532C017C for ; Wed, 8 May 2013 03:55:07 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=CxpJV9HVaGHaw50AnhnpDvxBDGH4hpuw1IW3Owari7TSvV IxWIRFlS67Ijkfdeaqu+rdcyM4fPRtSf5kaDNxxwlzOldRCPUr8Yio2RIbdDKouY gh6Ol6V1ihW42wNClebOFeWzO797yoiU2QZlREonFdB3pJmgRP9qKhOPVOnuI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=MJI2hIhItc04DNzyIVXy6fWWTpE=; b=HNPLcgwIWRTts6BCy4eA yT++5gXoBEWXv5UAA1nzC6mWVC9USC0kRlVLXVGjNFpAsgfyz7Pbs+OVeWYu3clC q6hjZKSGny+RP7uKr0MBegb8RGXGugip/spO2sPzeTFbKSWzZQ7L6aJe1/iXn/4O lqpnEs4EUqMNvAEuOBQSXfk= Received: (qmail 15957 invoked by alias); 7 May 2013 17:55:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15939 invoked by uid 89); 7 May 2013 17:54:58 -0000 X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_YE, SPF_PASS, TW_ZJ autolearn=ham version=3.3.1 Received: from mail-ob0-f174.google.com (HELO mail-ob0-f174.google.com) (209.85.214.174) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 07 May 2013 17:54:57 +0000 Received: by mail-ob0-f174.google.com with SMTP id dn14so830400obc.5 for ; Tue, 07 May 2013 10:54:55 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.149.129 with SMTP id ua1mr906499oeb.56.1367949295453; Tue, 07 May 2013 10:54:55 -0700 (PDT) Received: by 10.182.156.49 with HTTP; Tue, 7 May 2013 10:54:55 -0700 (PDT) Date: Tue, 7 May 2013 19:54:55 +0200 Message-ID: Subject: [PATCH 3/n, i386]: Merge and extend pextrb and pextrw vec_extract patterns From: Uros Bizjak To: "gcc-patches@gcc.gnu.org" X-Virus-Found: No Hello! Attached patch merges and extends pextrb and pextrw vec_extract patterns. Apart from merging where appropriate, the patch adds extractions to non-zero-extended registers and HI/QImode extractions from memory to integer registers. While playing with patch, a deficiency in how mode attributes are handled was discovered [1]. Mode attributes with specific mode iterator can not be used as mode iterators in *.md files, so *vec_extractv16qi_zext and *vec_extractv8hi_zext remain separate. 2013-05-07 Uros Bizjak * config/i386/sse.md (ssescalarnummask): New mode attribute. (PEXTR_MODE, PEXTR_MODEx): New mode iterators. (*vec_extract): Merge from *sse4_1_pextrb_memory and *sse4_1_pextrw_memory. Handle register target operands. (*vec_extractv8hi_sse2): New pattern. (*vec_extractv16qi_zext): Rename from *sse4_1_pextrb_. (*vec_extractv8hi_zext): Rename from *sse2_pextrw_. (*vec_extract_mem): New insn and split pattern. Patch was tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline. [1] http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57195 Uros. Index: sse.md =================================================================== --- sse.md (revision 198685) +++ sse.md (working copy) @@ -362,6 +362,13 @@ (V8SF "8") (V4DF "4") (V4SF "4") (V2DF "2")]) +;; Mask of scalar elements in each vector type +(define_mode_attr ssescalarnummask + [(V32QI "31") (V16HI "15") (V8SI "7") (V4DI "3") + (V16QI "15") (V8HI "7") (V4SI "3") (V2DI "1") + (V8SF "7") (V4DF "3") + (V4SF "3") (V2DF "1")]) + ;; SSE prefix for integer vector modes (define_mode_attr sseintprefix [(V2DI "p") (V2DF "") @@ -6933,60 +6940,6 @@ (set_attr "prefix" "orig,orig,vex,vex") (set_attr "mode" "TI")]) -(define_insn "*sse4_1_pextrb_" - [(set (match_operand:SWI48 0 "register_operand" "=r") - (zero_extend:SWI48 - (vec_select:QI - (match_operand:V16QI 1 "register_operand" "x") - (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))] - "TARGET_SSE4_1" - "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "TI")]) - -(define_insn "*sse4_1_pextrb_memory" - [(set (match_operand:QI 0 "memory_operand" "=m") - (vec_select:QI - (match_operand:V16QI 1 "register_operand" "x") - (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")])))] - "TARGET_SSE4_1" - "%vpextrb\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "TI")]) - -(define_insn "*sse2_pextrw_" - [(set (match_operand:SWI48 0 "register_operand" "=r") - (zero_extend:SWI48 - (vec_select:HI - (match_operand:V8HI 1 "register_operand" "x") - (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))] - "TARGET_SSE2" - "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "TI")]) - -(define_insn "*sse4_1_pextrw_memory" - [(set (match_operand:HI 0 "memory_operand" "=m") - (vec_select:HI - (match_operand:V8HI 1 "register_operand" "x") - (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")])))] - "TARGET_SSE4_1" - "%vpextrw\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_extra" "1") - (set_attr "length_immediate" "1") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "TI")]) - (define_expand "avx2_pshufdv3" [(match_operand:V8SI 0 "register_operand") (match_operand:V8SI 1 "nonimmediate_operand") @@ -7315,14 +7268,107 @@ (set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex") (set_attr "mode" "TI,TI,V4SF,SF,SF")]) +;; Modes handled by pextr patterns. +(define_mode_iterator PEXTR_MODEx + [V16QI V8HI]) + +(define_mode_iterator PEXTR_MODE + [(V16QI "TARGET_SSE4_1") V8HI]) + +(define_insn "*vec_extract" + [(set (match_operand: 0 "nonimmediate_operand" "=r,m") + (vec_select: + (match_operand:PEXTR_MODE 1 "register_operand" "x,x") + (parallel + [(match_operand:SI 2 "const_0_to__operand")])))] + "TARGET_SSE4_1" + "@ + %vpextr\t{%2, %1, %k0|%k0, %1, %2} + %vpextr\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sselog1") + (set (attr "prefix_data16") + (if_then_else + (and (eq_attr "alternative" "0") + (eq (const_string "mode") (const_string "V8HImode"))) + (const_string "1") + (const_string "*"))) + (set (attr "prefix_extra") + (if_then_else + (and (eq_attr "alternative" "0") + (eq (const_string "mode") (const_string "V8HImode"))) + (const_string "*") + (const_string "1"))) + (set_attr "length_immediate" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + +(define_insn "*vec_extractv8hi_sse2" + [(set (match_operand:HI 0 "register_operand" "=r") + (vec_select:HI + (match_operand:V8HI 1 "register_operand" "x") + (parallel + [(match_operand:SI 2 "const_0_to_7_operand")])))] + "TARGET_SSE2 && !TARGET_SSE4_1" + "pextrw\t{%2, %1, %k0|%k0, %1, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_data16" "1") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + +(define_insn "*vec_extractv16qi_zext" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (zero_extend:SWI48 + (vec_select:QI + (match_operand:V16QI 1 "register_operand" "x") + (parallel + [(match_operand:SI 2 "const_0_to_15_operand")]))))] + "TARGET_SSE4_1" + "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + +(define_insn "*vec_extractv8hi_zext" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (zero_extend:SWI48 + (vec_select:HI + (match_operand:V8HI 1 "register_operand" "x") + (parallel + [(match_operand:SI 2 "const_0_to_7_operand")]))))] + "TARGET_SSE2" + "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_data16" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + +(define_insn_and_split "*vec_extract_mem" + [(set (match_operand: 0 "register_operand" "=r") + (vec_select: + (match_operand:PEXTR_MODEx 1 "memory_operand" "o") + (parallel + [(match_operand 2 "const_0_to__operand")])))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 1))] +{ + int offs = INTVAL (operands[2]) * GET_MODE_SIZE (mode); + + operands[1] = adjust_address (operands[1], mode, offs); +}) + (define_insn "*vec_extract_0" - [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,r,x ,m,r") + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r ,r,x ,m") (vec_select:SWI48 - (match_operand: 1 "nonimmediate_operand" "Yj,x,xm,x,m") + (match_operand: 1 "nonimmediate_operand" "mYj,x,xm,x") (parallel [(const_int 0)])))] "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" - [(set_attr "isa" "*,sse4,*,*,*")]) + [(set_attr "isa" "*,sse4,*,*")]) (define_insn "*vec_extractv2di_0_sse" [(set (match_operand:DI 0 "nonimmediate_operand" "=x,m")