Message ID | CAAgBjMktWM0xzyW9DVZy=1U3LoTGhbFW_sPrbYiPODZ3YPud2g@mail.gmail.com |
---|---|
State | New |
Headers | show |
Series | Adjust affected targets for vec_perm_const hook | expand |
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> writes: > Hi Richard, > The attached patch addresses formatting nits for affected targets. > Tested with make all-gcc stage1 (except for gcn). OK, thanks. > Sorry if this sounds like a naive question, but what target triplet > should I use to build gcn port ? I think it's amdgcn-amdhsa. Richard > Thanks, > Prathamesh > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index f4d2a800f39..e6a24a0f9e1 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -24145,9 +24145,13 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) > /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ > > static bool > -aarch64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel) > +aarch64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > struct expand_vec_perm_d d; > > /* Check whether the mask can be applied to a single vector. */ > diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc > index 2afe0445ed5..70c2d50f0cc 100644 > --- a/gcc/config/arm/arm.cc > +++ b/gcc/config/arm/arm.cc > @@ -31813,9 +31813,13 @@ arm_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) > /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ > > static bool > -arm_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, rtx op1, > +arm_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > struct expand_vec_perm_d d; > int i, nelt, which; > > diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc > index e2e9335ad75..4642d5d55bf 100644 > --- a/gcc/config/gcn/gcn.cc > +++ b/gcc/config/gcn/gcn.cc > @@ -4131,10 +4131,13 @@ gcn_make_vec_perm_address (unsigned int *perm) > permutations. */ > > static bool > -gcn_vectorize_vec_perm_const (machine_mode vmode, rtx dst, > - rtx src0, rtx src1, > +gcn_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx dst, rtx src0, rtx src1, > const vec_perm_indices & sel) > { > + if (vmode != op_mode) > + return false; > + > unsigned int nelt = GET_MODE_NUNITS (vmode); > > gcc_assert (VECTOR_MODE_P (vmode)); > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc > index 806e1f5aaa3..adf68547119 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -22060,9 +22060,13 @@ canonicalize_perm (struct expand_vec_perm_d *d) > /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ > > bool > -ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel) > +ix86_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > struct expand_vec_perm_d d; > unsigned char perm[MAX_VECT_LEN]; > unsigned int i, nelt, which; > diff --git a/gcc/config/i386/i386-expand.h b/gcc/config/i386/i386-expand.h > index 9d320c29552..6c650196c9c 100644 > --- a/gcc/config/i386/i386-expand.h > +++ b/gcc/config/i386/i386-expand.h > @@ -48,8 +48,9 @@ rtx gen_push (rtx arg); > rtx gen_pop (rtx arg); > rtx ix86_expand_builtin (tree exp, rtx target, rtx subtarget, > machine_mode mode, int ignore); > -bool ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel); > +bool ix86_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel); > bool ix86_notrack_prefixed_insn_p (rtx_insn *); > machine_mode ix86_split_reduction (machine_mode mode); > void ix86_expand_divmod_libfunc (rtx libfunc, machine_mode mode, rtx op0, > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 175ce013e5d..50112a8efee 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -15836,7 +15836,7 @@ > sel[7] = 15; > } > vec_perm_indices indices (sel, 2, 8); > - bool ok = targetm.vectorize.vec_perm_const (V8SImode, target, > + bool ok = targetm.vectorize.vec_perm_const (V8SImode, V8SImode, target, > arg0, arg1, indices); > gcc_assert (ok); > emit_move_insn (operands[0], > @@ -24569,7 +24569,7 @@ > sel[3] = 7; > } > vec_perm_indices indices (sel, arg0 != arg1 ? 2 : 1, 4); > - bool ok = targetm.vectorize.vec_perm_const (V4SImode, target, > + bool ok = targetm.vectorize.vec_perm_const (V4SImode, V4SImode, target, > arg0, arg1, indices); > gcc_assert (ok); > emit_move_insn (operands[0], > diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc > index f9fb681a36c..25e4a47e363 100644 > --- a/gcc/config/ia64/ia64.cc > +++ b/gcc/config/ia64/ia64.cc > @@ -332,8 +332,8 @@ static fixed_size_mode ia64_get_reg_raw_mode (int regno); > static section * ia64_hpux_function_section (tree, enum node_frequency, > bool, bool); > > -static bool ia64_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, > - const vec_perm_indices &); > +static bool ia64_vectorize_vec_perm_const (machine_mode, machine_mode, rtx, > + rtx, rtx, const vec_perm_indices &); > > static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode); > static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode); > @@ -11751,9 +11751,13 @@ ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) > /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ > > static bool > -ia64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel) > +ia64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > struct expand_vec_perm_d d; > unsigned char perm[MAX_VECT_LEN]; > unsigned int i, nelt, which; > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc > index e64928f4113..5eb845960e1 100644 > --- a/gcc/config/mips/mips.cc > +++ b/gcc/config/mips/mips.cc > @@ -21790,9 +21790,13 @@ mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) > /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ > > static bool > -mips_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel) > +mips_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > struct expand_vec_perm_d d; > int i, nelt, which; > unsigned char orig_perm[MAX_VECT_LEN]; > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index d4defc855d0..0af2085adc0 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -23294,9 +23294,13 @@ rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1, > /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ > > static bool > -rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel) > +rs6000_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > bool testing_p = !target; > > /* AltiVec (and thus VSX) can handle arbitrary permutations. */ > diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc > index 45bbb6c3d70..fa1b6deff9b 100644 > --- a/gcc/config/s390/s390.cc > +++ b/gcc/config/s390/s390.cc > @@ -17175,9 +17175,13 @@ vectorize_vec_perm_const_1 (const struct expand_vec_perm_d &d) > hook is supposed to emit the required INSNs. */ > > bool > -s390_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, rtx op1, > +s390_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > struct expand_vec_perm_d d; > unsigned int i, nelt; > > diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc > index aca925befe1..c72c38e1999 100644 > --- a/gcc/config/sparc/sparc.cc > +++ b/gcc/config/sparc/sparc.cc > @@ -712,7 +712,8 @@ static bool sparc_modes_tieable_p (machine_mode, machine_mode); > static bool sparc_can_change_mode_class (machine_mode, machine_mode, > reg_class_t); > static HOST_WIDE_INT sparc_constant_alignment (const_tree, HOST_WIDE_INT); > -static bool sparc_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, > +static bool sparc_vectorize_vec_perm_const (machine_mode, machine_mode, > + rtx, rtx, rtx, > const vec_perm_indices &); > static bool sparc_can_follow_jump (const rtx_insn *, const rtx_insn *); > static HARD_REG_SET sparc_zero_call_used_regs (HARD_REG_SET); > @@ -13035,9 +13036,13 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) > /* Implement TARGET_VEC_PERM_CONST. */ > > static bool > -sparc_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, > - rtx op1, const vec_perm_indices &sel) > +sparc_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > + rtx target, rtx op0, rtx op1, > + const vec_perm_indices &sel) > { > + if (vmode != op_mode) > + return false; > + > if (!TARGET_VIS2) > return false; >
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index f4d2a800f39..e6a24a0f9e1 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -24145,9 +24145,13 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -aarch64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel) +aarch64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + struct expand_vec_perm_d d; /* Check whether the mask can be applied to a single vector. */ diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 2afe0445ed5..70c2d50f0cc 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -31813,9 +31813,13 @@ arm_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -arm_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, rtx op1, +arm_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + struct expand_vec_perm_d d; int i, nelt, which; diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index e2e9335ad75..4642d5d55bf 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -4131,10 +4131,13 @@ gcn_make_vec_perm_address (unsigned int *perm) permutations. */ static bool -gcn_vectorize_vec_perm_const (machine_mode vmode, rtx dst, - rtx src0, rtx src1, +gcn_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx dst, rtx src0, rtx src1, const vec_perm_indices & sel) { + if (vmode != op_mode) + return false; + unsigned int nelt = GET_MODE_NUNITS (vmode); gcc_assert (VECTOR_MODE_P (vmode)); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 806e1f5aaa3..adf68547119 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -22060,9 +22060,13 @@ canonicalize_perm (struct expand_vec_perm_d *d) /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ bool -ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel) +ix86_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + struct expand_vec_perm_d d; unsigned char perm[MAX_VECT_LEN]; unsigned int i, nelt, which; diff --git a/gcc/config/i386/i386-expand.h b/gcc/config/i386/i386-expand.h index 9d320c29552..6c650196c9c 100644 --- a/gcc/config/i386/i386-expand.h +++ b/gcc/config/i386/i386-expand.h @@ -48,8 +48,9 @@ rtx gen_push (rtx arg); rtx gen_pop (rtx arg); rtx ix86_expand_builtin (tree exp, rtx target, rtx subtarget, machine_mode mode, int ignore); -bool ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel); +bool ix86_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel); bool ix86_notrack_prefixed_insn_p (rtx_insn *); machine_mode ix86_split_reduction (machine_mode mode); void ix86_expand_divmod_libfunc (rtx libfunc, machine_mode mode, rtx op0, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 175ce013e5d..50112a8efee 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15836,7 +15836,7 @@ sel[7] = 15; } vec_perm_indices indices (sel, 2, 8); - bool ok = targetm.vectorize.vec_perm_const (V8SImode, target, + bool ok = targetm.vectorize.vec_perm_const (V8SImode, V8SImode, target, arg0, arg1, indices); gcc_assert (ok); emit_move_insn (operands[0], @@ -24569,7 +24569,7 @@ sel[3] = 7; } vec_perm_indices indices (sel, arg0 != arg1 ? 2 : 1, 4); - bool ok = targetm.vectorize.vec_perm_const (V4SImode, target, + bool ok = targetm.vectorize.vec_perm_const (V4SImode, V4SImode, target, arg0, arg1, indices); gcc_assert (ok); emit_move_insn (operands[0], diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc index f9fb681a36c..25e4a47e363 100644 --- a/gcc/config/ia64/ia64.cc +++ b/gcc/config/ia64/ia64.cc @@ -332,8 +332,8 @@ static fixed_size_mode ia64_get_reg_raw_mode (int regno); static section * ia64_hpux_function_section (tree, enum node_frequency, bool, bool); -static bool ia64_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, - const vec_perm_indices &); +static bool ia64_vectorize_vec_perm_const (machine_mode, machine_mode, rtx, + rtx, rtx, const vec_perm_indices &); static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode); static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode); @@ -11751,9 +11751,13 @@ ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -ia64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel) +ia64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + struct expand_vec_perm_d d; unsigned char perm[MAX_VECT_LEN]; unsigned int i, nelt, which; diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index e64928f4113..5eb845960e1 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -21790,9 +21790,13 @@ mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -mips_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel) +mips_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + struct expand_vec_perm_d d; int i, nelt, which; unsigned char orig_perm[MAX_VECT_LEN]; diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d4defc855d0..0af2085adc0 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -23294,9 +23294,13 @@ rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1, /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel) +rs6000_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + bool testing_p = !target; /* AltiVec (and thus VSX) can handle arbitrary permutations. */ diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index 45bbb6c3d70..fa1b6deff9b 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -17175,9 +17175,13 @@ vectorize_vec_perm_const_1 (const struct expand_vec_perm_d &d) hook is supposed to emit the required INSNs. */ bool -s390_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, rtx op1, +s390_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + struct expand_vec_perm_d d; unsigned int i, nelt; diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc index aca925befe1..c72c38e1999 100644 --- a/gcc/config/sparc/sparc.cc +++ b/gcc/config/sparc/sparc.cc @@ -712,7 +712,8 @@ static bool sparc_modes_tieable_p (machine_mode, machine_mode); static bool sparc_can_change_mode_class (machine_mode, machine_mode, reg_class_t); static HOST_WIDE_INT sparc_constant_alignment (const_tree, HOST_WIDE_INT); -static bool sparc_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, +static bool sparc_vectorize_vec_perm_const (machine_mode, machine_mode, + rtx, rtx, rtx, const vec_perm_indices &); static bool sparc_can_follow_jump (const rtx_insn *, const rtx_insn *); static HARD_REG_SET sparc_zero_call_used_regs (HARD_REG_SET); @@ -13035,9 +13036,13 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) /* Implement TARGET_VEC_PERM_CONST. */ static bool -sparc_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, - rtx op1, const vec_perm_indices &sel) +sparc_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { + if (vmode != op_mode) + return false; + if (!TARGET_VIS2) return false;