From patchwork Sun Aug 6 19:04:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 798441 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-459902-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cY8oSVUt"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xQVSw3kY3z9s8P for ; Mon, 7 Aug 2017 05:04:15 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=YZp5+PL+sWulEVOzZOcCVmwA3WJRp197vdUoedPGraEaLq RjGBpkk4+RggoRMu6z7nAaiy6KFo45oevEKIUlkxu0brw3ofW6N4FTi00SrVsF5t scsZVVRsbSE9FQFMXUMjrYWsBQ1cCnMKEriJLreU/BZCoTjiTnaU6zZKvnHYI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=k7o4+Vzyp7I2q3Cqmdl/+LmSnyk=; b=cY8oSVUtvedgNSkC6FLa icmT7rwMSCyj9GcQ0lklvUN3C8PfXdU6sJ85FX0JAab6bgwbht2xPMOM6Uh5+L4V Lb2BHezUBi8DmqV3wuXKUNX1kON/xbFMHwCz462Y/icnyPWa3xwX2wdPB+d1Z7Nd VvA64CmIRSVMtzp0iSDo8sI= Received: (qmail 122650 invoked by alias); 6 Aug 2017 19:04:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 122628 invoked by uid 89); 6 Aug 2017 19:04:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-yw0-f182.google.com Received: from mail-yw0-f182.google.com (HELO mail-yw0-f182.google.com) (209.85.161.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 06 Aug 2017 19:04:04 +0000 Received: by mail-yw0-f182.google.com with SMTP id p68so32777508ywg.0 for ; Sun, 06 Aug 2017 12:04:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=DDod/GhHrFbpwOQkThYgexSnaQoIDPgrV7BYG2W2fPA=; b=CgA8sx98kjUvl7su27POUi+aECTttJv5mJmekilDEschIEckTOENSiwPomhtZWmnu7 RUDKyhOmNMRfzML/UCSwE+7Atdyc0/+S8cNbnVg2ZXtgLmhvFbWzVbyCzxdTCGIz8amZ mNCFeu2LY+xw6D9zb01nfvy9Kj3CprRGIP2gzWRLFf5Tx/RtvE+jW/rpnaWOEQNG2qxi XR/61YLcAYcJnH93i57wEkH3Xsd+5128Przzm4MJu22ndYgdIvwvmlt3xaKmES3dDuEU 9SwAhV3FzP+nC7w3itPruwSDC4jyp95H6w+kRc2sjuoaHFu5jrHy4vTDKYsrtubpaTzN tirg== X-Gm-Message-State: AIVw112d0woGvC2d5NOvxROS6UG7PDSP/vssIohHdCI3QPIrTUbxv2Y7 Wh+Wop0aJt76Wq+kcFVBwklgpNbUpHrc X-Received: by 10.129.78.206 with SMTP id c197mr7111131ywb.455.1502046242362; Sun, 06 Aug 2017 12:04:02 -0700 (PDT) MIME-Version: 1.0 Received: by 10.129.84.85 with HTTP; Sun, 6 Aug 2017 12:04:01 -0700 (PDT) From: Andrew Pinski Date: Sun, 6 Aug 2017 12:04:01 -0700 Message-ID: Subject: [Committed] Fix testsuite/gcc.target/aarch64/target_attr*.c testcases when -mcpu= or -march= supplied To: GCC Patches X-IsSubscribed: yes These testcase assume -mcpu=generic or -march=armv8.1-a so use those options as needed. Note gcc.target/aarch64/target_attr_3.c needs both as it depends on scheduler to get the pattern needed for fix-cortex-a53-835769 to work. Committed after testing on aarch64-linux-gnu with --target_board=unix/\{,-mcpu=thunderx,-mcpu=thunderx2t99,-march=armv8-a,-march=armv8.1-a,-march=armv8.2-a\} and saw no failures. Thanks, Andrew Pinski ChangeLog: * gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic. * gcc.target/aarch64/target_attr_13.c: LIkewise. * gcc.target/aarch64/target_attr_15.c: LIkewise. * gcc.target/aarch64/target_attr_4.c: Likewise. * gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a. * gcc.target/aarch64/target_attr_2.c: Likewise. * gcc.target/aarch64/target_attr_7.c: Likewise. * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise. * gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise. * gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a. Index: testsuite/gcc.target/aarch64/target_attr_10.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_10.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_10.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=armv8-a+simd" } */ +/* { dg-options "-O2 -march=armv8-a+simd -mcpu=generic" } */ /* Using a SIMD intrinsic from a function tagged with nosimd should fail due to inlining rules. */ Index: testsuite/gcc.target/aarch64/target_attr_13.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_13.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_13.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */ +/* { dg-options "-O2 -march=armv8-a+crc+crypto -mcpu=generic" } */ #include "arm_acle.h" Index: testsuite/gcc.target/aarch64/target_attr_15.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_15.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_15.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-march=armv8-a+crypto -save-temps" } */ +/* { dg-options "-march=armv8-a+crypto -mcpu=generic -save-temps" } */ /* Check that "+nothing" clears the ISA flags. */ Index: testsuite/gcc.target/aarch64/target_attr_1.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_1.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_1.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx -dA" } */ +/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */ /* Test that cpu attribute overrides the command-line -mcpu. */ Index: testsuite/gcc.target/aarch64/target_attr_2.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_2.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_2.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -march=armv8-a -ftree-vectorize -fdump-tree-vect-all" } */ /* The various ways to turn off simd availability should turn off vectorization. */ Index: testsuite/gcc.target/aarch64/target_attr_3.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_3.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_3.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */ +/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -march=armv8-a -mcpu=generic -save-temps" } */ /* Check that the attribute overrides the command line option and the fix is applied once. */ Index: testsuite/gcc.target/aarch64/target_attr_4.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_4.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_4.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */ +/* { dg-options "-O2 -march=armv8-a+nocrc -mcpu=generic -save-temps" } */ #include "arm_acle.h" Index: testsuite/gcc.target/aarch64/target_attr_7.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_7.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_7.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx -dA" } */ +/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */ /* Make sure that #pragma overrides command line option and target attribute overrides the pragma. */ Index: testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ #include "arm_neon.h" Index: testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c =================================================================== --- testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c (revision 250901) +++ testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ /* Make sure that we don't ICE when dealing with vector parameters in a simd-tagged function within a non-simd translation unit. */