From patchwork Wed Oct 30 03:03:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Stump X-Patchwork-Id: 287120 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2391C2C011C for ; Wed, 30 Oct 2013 14:03:15 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :content-type:mime-version:subject:from:in-reply-to:date:cc :message-id:references:to; q=dns; s=default; b=dL4SVGauDNd3RJis/ od+263fcy6IejdBQEIjhmGnk4mvj/qNcSFvMEJfQWtti1Nv1869oaMnbCdVXedMa r+UvvjrfsV0sofe2rF/S4+SHsMQeVNa4E/wvyt4AYvi/xo7qYIm7W+4UzuT31qf7 fMYQ+mOKQpB2hIGRLfQ5o9gg2U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :content-type:mime-version:subject:from:in-reply-to:date:cc :message-id:references:to; s=default; bh=vLPZ8eTusZ197escC2ts2q8 SoRQ=; b=vma4zTjbHPCAu8Nt90U0BSjCM3RmbZ2lJKPeJRgruvTX4DA/xyaK48Y 73wIJAOcpcWYF+5KkcKzWXRLC64iO6/i5KDldyaLex+tyIn/FY4/atypkk0gTaVk C/5PPebQPQ2stGwZe40AOQ9WzQLXuw5BH/9R+dfvdITDTZluUvdI= Received: (qmail 15214 invoked by alias); 30 Oct 2013 03:03:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15196 invoked by uid 89); 30 Oct 2013 03:03:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: qmta02.emeryville.ca.mail.comcast.net Received: from qmta02.emeryville.ca.mail.comcast.net (HELO qmta02.emeryville.ca.mail.comcast.net) (76.96.30.24) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 30 Oct 2013 03:03:05 +0000 Received: from omta07.emeryville.ca.mail.comcast.net ([76.96.30.59]) by qmta02.emeryville.ca.mail.comcast.net with comcast id jEmR1m0021GXsucA2F34yi; Wed, 30 Oct 2013 03:03:04 +0000 Received: from up.mrs.kithrup.com ([24.4.193.8]) by omta07.emeryville.ca.mail.comcast.net with comcast id jF331m00A0BKwT48UF33Av; Wed, 30 Oct 2013 03:03:03 +0000 Mime-Version: 1.0 (Mac OS X Mail 6.6 \(1510\)) Subject: Re: Using gen_int_mode instead of GEN_INT minor testsuite fallout on MIPS From: Mike Stump In-Reply-To: Date: Tue, 29 Oct 2013 20:03:03 -0700 Cc: GCC Patches Message-Id: References: <1378833157-11511-1-git-send-email-james.greenhalgh@arm.com> <87y574mr2h.fsf@talisman.default> <1378900963.71148.YahooMailNeo@web87402.mail.ir2.yahoo.com> <87y573kxse.fsf@talisman.default> <87ppseko71.fsf@talisman.default> <87d2odkuu7.fsf@talisman.default> <0F11E779-5DA9-43E6-A12F-64A66B147AF7@comcast.net> <792D0DC7-4751-438F-A40A-94168CBA7F9E@comcast.net> <201309170341.r8H3fnTD032129@greed.delorie.com> <87txhjic2a.fsf@talisman.default> <74570B57-AF73-4FD8-B5D1-A970A02AA22B@comcast.net> To: Richard Biener X-IsSubscribed: yes On Oct 29, 2013, at 3:20 AM, Richard Biener wrote: > Can you please get rid of PARTIAL_INT_MODE_NAME by > making the name a required argument to PARTIAL_INT_MODE? Sure, easy to do. * machmode.def (PARTIAL_INT_MODE): Add precision and name. * genmodes.c (PARTIAL_INT_MODE): Add precision and name. (make_vector_mode): Increase namebuf to 16. (emit_insn_modes_h): When processing BImode, don't also match partial int modes. (emit_class_narrowest_mode): Likewise. * config/bfin/bfin-modes.def: Add precision to PDI. * config/m32c/m32c-modes.def: Add precision to PSI. * config/msp430/msp430-modes.def: Add precision to PSI. * config/rs6000/rs6000-modes.def: Add precision to PTI. * config/sh/sh-modes.def: Add precision to PSI and PDI. Thanks for the review. Committed revision 204193. Index: config/bfin/bfin-modes.def =================================================================== --- config/bfin/bfin-modes.def (revision 204192) +++ config/bfin/bfin-modes.def (working copy) @@ -19,7 +19,7 @@ . */ /* PDImode for the 40-bit accumulators. */ -PARTIAL_INT_MODE (DI); +PARTIAL_INT_MODE (DI, 40, PDI); /* Two of those - covering both accumulators for vector multiplications. */ VECTOR_MODE (INT, PDI, 2); Index: config/m32c/m32c-modes.def =================================================================== --- config/m32c/m32c-modes.def (revision 204192) +++ config/m32c/m32c-modes.def (working copy) @@ -22,7 +22,7 @@ /*INT_MODE (PI, 3);*/ /* 24-bit pointers, in 32-bit units */ -PARTIAL_INT_MODE (SI); +PARTIAL_INT_MODE (SI, 24, PSI); /* 48-bit MULEX result */ /* INT_MODE (MI, 6); */ Index: config/msp430/msp430-modes.def =================================================================== --- config/msp430/msp430-modes.def (revision 204192) +++ config/msp430/msp430-modes.def (working copy) @@ -1,3 +1,3 @@ /* 20-bit address */ -PARTIAL_INT_MODE (SI); +PARTIAL_INT_MODE (SI, 20, PSI); Index: config/rs6000/rs6000-modes.def =================================================================== --- config/rs6000/rs6000-modes.def (revision 204192) +++ config/rs6000/rs6000-modes.def (working copy) @@ -45,4 +45,4 @@ VECTOR_MODES (FLOAT, 32); /* V /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ -PARTIAL_INT_MODE (TI); +PARTIAL_INT_MODE (TI, 128, PTI); Index: config/sh/sh-modes.def =================================================================== --- config/sh/sh-modes.def (revision 204192) +++ config/sh/sh-modes.def (working copy) @@ -18,9 +18,9 @@ along with GCC; see the file COPYING3. . */ /* The SH uses a partial integer mode to represent the FPSCR register. */ -PARTIAL_INT_MODE (SI); +PARTIAL_INT_MODE (SI, 22, PSI); /* PDI mode is used to represent a function address in a target register. */ -PARTIAL_INT_MODE (DI); +PARTIAL_INT_MODE (DI, 64, PDI); /* Vector modes. */ VECTOR_MODE (INT, QI, 2); /* V2QI */ Index: genmodes.c =================================================================== --- genmodes.c (revision 204192) +++ genmodes.c (working copy) @@ -644,10 +644,10 @@ reset_float_format (const char *name, co m->format = format; } -/* Partial integer modes are specified by relation to a full integer mode. - For now, we do not attempt to narrow down their bit sizes. */ -#define PARTIAL_INT_MODE(M) \ - make_partial_integer_mode (#M, "P" #M, -1U, __FILE__, __LINE__) +/* Partial integer modes are specified by relation to a full integer + mode. */ +#define PARTIAL_INT_MODE(M,PREC,NAME) \ + make_partial_integer_mode (#M, #NAME, PREC, __FILE__, __LINE__) static void ATTRIBUTE_UNUSED make_partial_integer_mode (const char *base, const char *name, unsigned int precision, @@ -684,7 +684,7 @@ make_vector_mode (enum mode_class bclass struct mode_data *v; enum mode_class vclass = vector_class (bclass); struct mode_data *component = find_mode (base); - char namebuf[8]; + char namebuf[16]; if (vclass == MODE_RANDOM) return; @@ -932,7 +932,7 @@ enum machine_mode\n{"); end will try to use it for bitfields in structures and the like, which we do not want. Only the target md file should generate BImode widgets. */ - if (first && first->precision == 1) + if (first && first->precision == 1 && c == MODE_INT) first = first->next; if (first && last) @@ -1202,7 +1202,7 @@ emit_class_narrowest_mode (void) /* Bleah, all this to get the comment right for MIN_MODE_INT. */ tagged_printf ("MIN_%s", mode_class_names[c], modes[c] - ? (modes[c]->precision != 1 + ? ((c != MODE_INT || modes[c]->precision != 1) ? modes[c]->name : (modes[c]->next ? modes[c]->next->name Index: machmode.def =================================================================== --- machmode.def (revision 204192) +++ machmode.def (working copy) @@ -121,11 +121,11 @@ along with GCC; see the file COPYING3. to FORMAT. Use in an ARCH-modes.def to reset the format of one of the float modes defined in this file. - PARTIAL_INT_MODE (MODE); + PARTIAL_INT_MODE (MODE, PRECISION, NAME); declares a mode of class PARTIAL_INT with the same size as - MODE (which must be an INT mode). The name of the new mode - is made by prefixing a P to the name MODE. This statement - may grow a PRECISION argument in the future. + MODE (which must be an INT mode) and precision PREC. + Optionally, NAME is the new name of the mode. NAME is the + name of the mode. VECTOR_MODE (CLASS, MODE, COUNT); Declare a vector mode whose component mode is MODE (of class