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Thu, 20 Jul 2017 12:49:03 +0000 From: Wilco Dijkstra To: GCC Patches , James Greenhalgh CC: nd Subject: [PATCH][AArch64] Improve addressing of TI/TFmode Date: Thu, 20 Jul 2017 12:49:03 +0000 Message-ID: authentication-results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM4PR08MB2659; 7:hHQOWPaH9Cd12L6j0Z74JDYsY70gb7sb/LLEP0lcZRtAPbpXjvTtCmVx/eR5DJxTcyNIbpHru2PjRry89XYi5ubrIIMlA/3Wb91lDRwBIOLu2B5U0c1CD28mi0p6dRiqkW0NQtYF+EKM2/zOijbQn4jdwFx2owaKVTSrAK5TXrkcvMqVqyTw7Q2HbHkRLd0J9tFE/+4ns11UI0CWjCnAKJ5ir2c/MFmyjG7h7/NIa1LJkr3sUAuIw/R0sXtoGc2CL1v+96kR/ciJFeS053gAPnDjJYLTHE8CoMsKG95XkJJiBfjnE30Qsk5CXKchf1Blkz7P/yC7jdHO4ESxKGke23zfI+eVnbsvNj1fQvUoX43zQ3tLczH8KwpNfTTtEq+PukX4zkTFaaGVKuzaJtQr9tv002V7D5Khr5NfGxDqqpAbbfbl6ezvaIQOyNYr9xuK1zQMvfvX4WTPMpTTY6zjZanef7yMLp++wT3YeogsZLhLuZaxD1YPhD1P+GbrhcVeo/kWXoR7tbk9VudoI4W4HPvYCYAqxwCEITfgTBL7yE0PG2YXClPJBdrKKkfIUr5jkmT2V5IcDbLgCC7K4AFjRx4z80PhNFutzK/U7pLvRc7UrZmbuFBUZRp79nQYnHpeskKpwm0a1l7rBBkkYX+nJI3jK5cfOjwHpmuMUOWHqGPt+ZM7Y1ieaG9qgWc50OQHp6qLmWC6N+M7bAmhDmfnpNCEuxnyZif1cWEotbhi5ZlUFIeSBfV8yFU6TZCtfIJmXtdr/1RVYODsbkE/3n1dkut2XWPgM7uDV65joQM8tdo= x-ms-office365-filtering-correlation-id: 5d9c9a43-64b7-4397-7511-08d4cf6db339 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; 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SRVR:AM4PR08MB2659; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM4PR08MB2659; x-forefront-prvs: 0374433C81 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39410400002)(39840400002)(39450400003)(39850400002)(39400400002)(39860400002)(377424004)(54356999)(55016002)(6116002)(966005)(3846002)(38730400002)(53936002)(189998001)(8676002)(9686003)(6306002)(25786009)(74316002)(6436002)(81166006)(99286003)(102836003)(575784001)(50986999)(86362001)(4326008)(5250100002)(8936002)(2900100001)(5660300001)(305945005)(6636002)(478600001)(3280700002)(66066001)(7696004)(14454004)(2906002)(3660700001)(72206003)(7736002)(6506006)(33656002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR08MB2659; H:AM5PR0802MB2610.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Jul 2017 12:49:03.0864 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR08MB2659 In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong pointed out some addressing inefficiencies due to a recent change in regcprop (https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00775.html). This patch improves aarch64_legitimize_address_displacement to split unaligned offsets of TImode and TFmode accesses. The resulting code is better and no longer relies on the original regcprop optimization. For the test we now produce: add x1, sp, 4 stp xzr, xzr, [x1, 24] rather than: mov x1, sp add x1, x1, 28 stp xzr, xzr, [x1] OK for commit? ChangeLog: 2017-06-20 Wilco Dijkstra * config/aarch64/aarch64.c (aarch64_legitimize_address_displacement): Improve unaligned TImode/TFmode base/offset split. testsuite * gcc.target/aarch64/ldp_stp_unaligned_2.c: New file. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 90f248025a4fa928ebac657b689010f74dd100b5..208fdbe7262a93ee8caada2868a8d447de619c6e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4705,15 +4705,17 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x, /* Split an out-of-range address displacement into a base and offset. Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise to increase opportunities for sharing the base address of different sizes. - For unaligned accesses and TI/TF mode use the signed 9-bit range. */ + Unaligned accesses use the signed 9-bit range, TImode/TFmode use + the intersection of signed scaled 7-bit and signed 9-bit offset. */ static bool aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode) { HOST_WIDE_INT offset = INTVAL (*disp); HOST_WIDE_INT base = offset & ~(GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3ffc); - if (mode == TImode || mode == TFmode - || (offset & (GET_MODE_SIZE (mode) - 1)) != 0) + if (mode == TImode || mode == TFmode) + base = (offset + 0x100) & ~0x1f8; + else if ((offset & (GET_MODE_SIZE (mode) - 1)) != 0) base = (offset + 0x100) & ~0x1ff; *off = GEN_INT (base); diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c new file mode 100644 index 0000000000000000000000000000000000000000..1e46755a39a0b97fa7af704086f82ffd5a216fb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c @@ -0,0 +1,18 @@ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +/* Check that we split unaligned LDP/STP into base and aligned offset. */ + +typedef struct +{ + int a, b, c, d, e; +} S; + +void foo (S *); + +void test (int x) +{ + S s = { .a = x }; + foo (&s); +} + +/* { dg-final { scan-assembler-not "mov\tx\[0-9\]+, sp" } } */