From patchwork Thu Jan 27 11:15:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 80651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 51E4A1007D1 for ; Thu, 27 Jan 2011 22:15:16 +1100 (EST) Received: (qmail 24296 invoked by alias); 27 Jan 2011 11:15:14 -0000 Received: (qmail 24287 invoked by uid 22791); 27 Jan 2011 11:15:13 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-fx0-f47.google.com (HELO mail-fx0-f47.google.com) (209.85.161.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 27 Jan 2011 11:15:08 +0000 Received: by fxm17 with SMTP id 17so1999876fxm.20 for ; Thu, 27 Jan 2011 03:15:05 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.95.203 with SMTP id e11mr779094fan.60.1296126905436; Thu, 27 Jan 2011 03:15:05 -0800 (PST) Received: by 10.223.70.129 with HTTP; Thu, 27 Jan 2011 03:15:05 -0800 (PST) In-Reply-To: References: Date: Thu, 27 Jan 2011 11:15:05 +0000 Message-ID: Subject: Re: [Patch wwwdocs] Update docs with respect to changes for ARM. From: Ramana Radhakrishnan To: Richard Earnshaw Cc: Gerald Pfeifer , gcc-patches X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Thu, Jan 27, 2011 at 12:10 AM, Richard Earnshaw wrote: > Ok with the various suggested changes. Thanks - this is what I committed. Ramana > > R. > > > > On 26 Jan 2011, at 22:55, "Gerald Pfeifer" wrote: > >> On Thu, 20 Jan 2011, Ramana Radhakrishnan wrote: >>> I think I've managed to scrub together all the relevant changes for >>> ARM for the past year and here's a patch that reflects it. >> >> Nice job!  Given how specific this is to ARM I'd like to defer the >> actual refer to Richard who has done this now. :-) >> >> From my side, only one most minor note: >> >> Index: ./htdocs/gcc-4.6/changes.html >> =================================================================== >> +    
  • Scheduling descriptions for the Cortex-M4, the Neon and >> +      the Floating point units of the Cortex-A9 and a pipeline >> +      description for the Cortex-A5 have been added.
    • >> >> "floating point units" (lower case F)? >> >> If Richard is fine, please apply. >> >> Thanks, >> Gerald >> > > Index: htdocs/gcc-4.6/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.6/changes.html,v retrieving revision 1.94 diff -a -u -r1.94 changes.html --- htdocs/gcc-4.6/changes.html 26 Jan 2011 17:07:00 -0000 1.94 +++ htdocs/gcc-4.6/changes.html 27 Jan 2011 11:14:00 -0000 @@ -617,11 +617,41 @@

    New Targets and Target Specific Improvements

    ARM

    -
      -
    • The SSA loop prefetching pass is enabled when - using -O3.
      • -
    • GCC now supports the Cortex-M4 processor - with -mcpu=cortex-m4.
      • +
    • GCC now supports the Cortex-M4 processor implementing + the v7-em version of the architecture using the option + -mcpu=cortex-m4.
      • + +
    • Scheduling descriptions for the Cortex-M4, the Neon and + the floating point units of the Cortex-A9 and a pipeline + description for the Cortex-A5 have been added.
      • + +
    • Synchronization primitives such as __sync_fetch_and_add + and friends are now inlined for supported architectures + rather than calling into a kernel helper function.
      • + +
    • SSA loop prefetching is enabled by default for the + Cortex-A9 at -O3.
      • + +
    • Several improvements were committed to improve code + generation for the ARM architecture including a rewritten + implementation for load and store multiples.
      • + +
    • Several enhancements were committed to improve SIMD code + generation for NEON by adding support for widening instructions, + misaligned loads and stores, vector conditionals and + support for 64 bit arithmetic.
      • + +
    • Support was added for the Faraday cores fa526, fa606te, + fa626te, fmp626te, fmp626 and fa726te and can be used with the + respective names as parameters to the -mcpu= + option.
      • + +
    • Basic support was added for Cortex-A15 and is available through + -mcpu=cortex-a15.
      • + +
    • GCC for AAPCS configurations now more closely adheres to the AAPCS + specification by enabling -fstrict-volatile-bitfields by + default.

    IA-32/x86-64