From patchwork Thu Jul 22 07:11:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carrot Wei X-Patchwork-Id: 59544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 267E2B70E3 for ; Thu, 22 Jul 2010 17:11:17 +1000 (EST) Received: (qmail 6881 invoked by alias); 22 Jul 2010 07:11:15 -0000 Received: (qmail 6868 invoked by uid 22791); 22 Jul 2010 07:11:13 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (216.239.44.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 22 Jul 2010 07:11:05 +0000 Received: from hpaq5.eem.corp.google.com (hpaq5.eem.corp.google.com [172.25.149.5]) by smtp-out.google.com with ESMTP id o6M7B3Tv008137 for ; Thu, 22 Jul 2010 00:11:03 -0700 Received: from yxi11 (yxi11.prod.google.com [10.190.3.11]) by hpaq5.eem.corp.google.com with ESMTP id o6M7AZ1v025990 for ; Thu, 22 Jul 2010 00:11:01 -0700 Received: by yxi11 with SMTP id 11so3282181yxi.34 for ; Thu, 22 Jul 2010 00:11:01 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.68.39 with SMTP id q39mr3615064yba.207.1279782661239; Thu, 22 Jul 2010 00:11:01 -0700 (PDT) Received: by 10.151.129.10 with HTTP; Thu, 22 Jul 2010 00:11:01 -0700 (PDT) Date: Thu, 22 Jul 2010 15:11:01 +0800 Message-ID: Subject: [PATCH: PR target/44999] Replace "and r0, r0, #255" with uxtb in thumb2 From: Carrot Wei To: gcc-patches@gcc.gnu.org X-System-Of-Record: true Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org In thumb2 "and r0, r0, #255" is 32 bit, uxtb is 16 bit and does the same operation. This patch simply detect the situation in pattern "andsi3" and call gen_thumb2_zero_extendqisi2_v6. Tested on arm qemu. ChangeLog: 2010-07-22 Wei Guozhi PR target/44999 * config/arm/arm.md (andsi3): Change to zero extension if possible. * config/arm/thumb2.md (thumb2_zero_extendqisi2_v6): Change the name. ChangeLog: 2010-07-22 Wei Guozhi PR target/44999 * gcc.target/arm/pr44999.c: New testcase. Index: thumb2.md =================================================================== --- thumb2.md (revision 162396) +++ thumb2.md (working copy) @@ -970,7 +970,7 @@ (set_attr "neg_pool_range" "*,250")] ) -(define_insn "*thumb2_zero_extendqisi2_v6" +(define_insn "thumb2_zero_extendqisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "TARGET_THUMB2 && arm_arch6" Index: arm.md =================================================================== --- arm.md (revision 162396) +++ arm.md (working copy) @@ -1933,9 +1933,16 @@ { if (GET_CODE (operands[2]) == CONST_INT) { - arm_split_constant (AND, SImode, NULL_RTX, - INTVAL (operands[2]), operands[0], - operands[1], optimize && can_create_pseudo_p ()); + if (INTVAL (operands[2]) == 255 && arm_arch6) + { + operands[1] = gen_rtx_SUBREG (QImode, operands[1], 0); + gen_thumb2_zero_extendqisi2_v6 (operands[0], operands[1]); + } + else + arm_split_constant (AND, SImode, NULL_RTX, + INTVAL (operands[2]), operands[0], + operands[1], + optimize && can_create_pseudo_p ()); DONE; } Index: pr44999.c =================================================================== --- pr44999.c (revision 0) +++ pr44999.c (revision 0) @@ -0,0 +1,7 @@ +/* { dg-options "-march=armv7-a -mthumb -Os" } */ +/* { dg-final { scan-assembler "uxtb" } } */ + +int tp(int x, int y) +{ + return (x & 0xff) - (y & 0xffff); +}