===================================================================
@@ -1493,7 +1493,8 @@ proc check_effective_target_vect_int { }
|| [istarget sparc*-*-*]
|| [istarget alpha*-*-*]
|| [istarget ia64-*-*]
- || [check_effective_target_arm32] } {
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
set et_vect_int_saved 1
}
}
@@ -2029,7 +2030,8 @@ proc check_effective_target_vect_shift {
|| [istarget ia64-*-*]
|| [istarget i?86-*-*]
|| [istarget x86_64-*-*]
- || [check_effective_target_arm32] } {
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
set et_vect_shift_saved 1
}
}
@@ -2143,7 +2145,8 @@ proc check_effective_target_vect_no_int_
set et_vect_no_int_max_saved 0
if { [istarget sparc*-*-*]
|| [istarget spu-*-*]
- || [istarget alpha*-*-*] } {
+ || [istarget alpha*-*-*]
+ || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
set et_vect_no_int_max_saved 1
}
}
@@ -2516,7 +2519,8 @@ proc check_effective_target_vect_no_alig
if { [istarget mipsisa64*-*-*]
|| [istarget sparc*-*-*]
|| [istarget ia64-*-*]
- || [check_effective_target_arm32] } {
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
set et_vect_no_align_saved 1
}
}