diff mbox series

rs6000: Some mfcr pattern simplification

Message ID 9824a76b35e13578df2ec49da6a126f3279d0edf.1538768001.git.segher@kernel.crashing.org
State New
Headers show
Series rs6000: Some mfcr pattern simplification | expand

Commit Message

Segher Boessenkool Oct. 5, 2018, 7:38 p.m. UTC 
2018-10-05  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator
	patterns): Merge SI and DI patterns to a GPR pattern.
	(unnamed define_insn and define_split for record form of that): Merge
	to a single define_insn_and_split pattern.

---
 gcc/config/rs6000/rs6000.md | 43 ++++++++++---------------------------------
 1 file changed, 10 insertions(+), 33 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5db3e57..0e7cf35 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11765,10 +11765,10 @@  (define_insn_and_split "*cmp<mode>_internal2"
 ;; cases the insns below which don't use an intermediate CR field will
 ;; be used instead.
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator:SI 1 "scc_comparison_operator"
-			   [(match_operand 2 "cc_reg_operand" "y")
-			    (const_int 0)]))]
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+	(match_operator:GPR 1 "scc_comparison_operator"
+			    [(match_operand 2 "cc_reg_operand" "y")
+			     (const_int 0)]))]
   ""
   "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
   [(set (attr "type")
@@ -11778,21 +11778,7 @@  (define_insn ""
 	(const_string "mfcr")))
    (set_attr "length" "8")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(match_operator:DI 1 "scc_comparison_operator"
-			   [(match_operand 2 "cc_reg_operand" "y")
-			    (const_int 0)]))]
-  "TARGET_POWERPC64"
-  "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
-  [(set (attr "type")
-     (cond [(match_test "TARGET_MFCRF")
-		(const_string "mfcrf")
-	   ]
-	(const_string "mfcr")))
-   (set_attr "length" "8")])
-
-(define_insn ""
+(define_insn_and_split ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC (match_operator:SI 1 "scc_comparison_operator"
 				       [(match_operand 2 "cc_reg_operand" "y,y")
@@ -11804,25 +11790,16 @@  (define_insn ""
   "@
    mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
    #"
-  [(set_attr "type" "shift")
-   (set_attr "dot" "yes")
-   (set_attr "length" "8,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand")
-	(compare:CC (match_operator:SI 1 "scc_comparison_operator"
-				       [(match_operand 2 "cc_reg_operand")
-					(const_int 0)])
-		    (const_int 0)))
-   (set (match_operand:SI 3 "gpc_reg_operand")
-	(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
-  "TARGET_32BIT && reload_completed"
+  "&& reload_completed"
   [(set (match_dup 3)
 	(match_op_dup 1 [(match_dup 2) (const_int 0)]))
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
 		    (const_int 0)))]
-  "")
+  ""
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
+   (set_attr "length" "8,16")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")