From patchwork Sat Jun 19 07:34:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 1494601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=y6Slz4WD; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G6SHT6D3qz9s5R for ; Sat, 19 Jun 2021 17:34:59 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3827E394342C for ; Sat, 19 Jun 2021 07:34:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3827E394342C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1624088089; bh=n2S31kpDKSO69CYXdHKkn/7KqeajzB785JoprTExljs=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=y6Slz4WDMOcCvmdarxKmmvxx57Bj9bogIPkSOZ3J3b5BRybYvIqTVpqosnOstpdSM ZCV4xUSL2npU/Vq4Q+/S5chbhoBYMmZyeQIRr9iv9nreM+UX51Bhxb75RfPNEejK3u yLmMezuf0B3mQmXP78ih0cPuXDXsv6Et9RwaRkoo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mengyan1223.wang (mengyan1223.wang [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 0EB48385482F for ; Sat, 19 Jun 2021 07:34:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0EB48385482F Received: from [IPv6:240e:35a:1006:1c00:dc73:854d:832e:3] (unknown [IPv6:240e:35a:1006:1c00:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384)) (Client did not present a certificate) (Authenticated sender: xry111@mengyan1223.wang) by mengyan1223.wang (Postfix) with ESMTPSA id 49AA565AD4; Sat, 19 Jun 2021 03:34:25 -0400 (EDT) Message-ID: <92711c73eb79a6c0bf69b3b86dff9a8575fab081.camel@mengyan1223.wang> Subject: [PATCH] mips: check MSA support for vector modes [PR100760,PR100761,PR100762] To: gcc-patches@gcc.gnu.org Date: Sat, 19 Jun 2021 15:34:22 +0800 User-Agent: Evolution 3.40.2 MIME-Version: 1.0 X-Spam-Status: No, score=-3038.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Cc: xry111@mengyan1223.wang Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Check if the vector mode is really supported by MSA in certain cases, instead of testing ISA_HAS_MSA. Simply testing ISA_HAS_MSA can cause ICE when MSA is enabled besides other MIPS SIMD extensions (notably, Loongson MMI). Bootstrapped and tested on mips64el-linux-gnu. OK to commit? gcc/ * config/mips/mips.c (mips_const_insns): Use MSA_SUPPORTED_MODE_P instead of ISA_HAS_MSA. (mips_expand_vec_unpack): Likewise. (mips_expand_vector_init): Likewise. gcc/testsuite/ * testsuite/gcc.target/mips/pr100760.c: New test. * testsuite/gcc.target/mips/pr100761.c: New test. * testsuite/gcc.target/mips/pr100762.c: New test. --- gcc/config/mips/mips.c | 6 +++--- gcc/testsuite/gcc.target/mips/pr100760.c | 10 ++++++++++ gcc/testsuite/gcc.target/mips/pr100761.c | 17 ++++++++++++++++ gcc/testsuite/gcc.target/mips/pr100762.c | 25 ++++++++++++++++++++++++ 4 files changed, 55 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/pr100760.c create mode 100644 gcc/testsuite/gcc.target/mips/pr100761.c create mode 100644 gcc/testsuite/gcc.target/mips/pr100762.c diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 1f1475cf400..00a8eef96aa 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -2879,7 +2879,7 @@ mips_const_insns (rtx x) return mips_build_integer (codes, INTVAL (x)); case CONST_VECTOR: - if (ISA_HAS_MSA + if (MSA_SUPPORTED_MODE_P (GET_MODE (x)) && mips_const_vector_same_int_p (x, GET_MODE (x), -512, 511)) return 1; /* Fall through. */ @@ -21732,7 +21732,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) rtx (*cmpFunc) (rtx, rtx, rtx); rtx tmp, dest, zero; - if (ISA_HAS_MSA) + if (MSA_SUPPORTED_MODE_P (imode)) { switch (imode) { @@ -21994,7 +21994,7 @@ mips_expand_vector_init (rtx target, rtx vals) all_same = false; } - if (ISA_HAS_MSA) + if (MSA_SUPPORTED_MODE_P (vmode)) { if (all_same) { diff --git a/gcc/testsuite/gcc.target/mips/pr100760.c b/gcc/testsuite/gcc.target/mips/pr100760.c new file mode 100644 index 00000000000..d715b85e790 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr100760.c @@ -0,0 +1,10 @@ +/* PR target/100760 + This was triggering an ICE with "maximum number of generated reload + insns per insn achieved (90)" when compiled with -mmsa -mloongson-mmi. */ + +/* { dg-do compile } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT32_TYPE__ int32_t; +typedef int32_t a __attribute__((__vector_size__(8))); +void b() { a x = (a){1, 1}; } diff --git a/gcc/testsuite/gcc.target/mips/pr100761.c b/gcc/testsuite/gcc.target/mips/pr100761.c new file mode 100644 index 00000000000..cc2598ee023 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr100761.c @@ -0,0 +1,17 @@ +/* PR target/100761 + This was triggering an ICE in mips_expand_vec_unpack when compiled with + -mmsa -mloongson-mmi. */ + +/* { dg-do compile } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT8_TYPE__ int8_t; +typedef __INT16_TYPE__ int16_t; +typedef int8_t i8x8 __attribute__((__vector_size__(8))); +typedef int16_t i16x8 __attribute__((__vector_size__(16))); + +i8x8 a; + +void f() { + i16x8 b = __builtin_convertvector (a, i16x8); +} diff --git a/gcc/testsuite/gcc.target/mips/pr100762.c b/gcc/testsuite/gcc.target/mips/pr100762.c new file mode 100644 index 00000000000..89c1185317c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr100762.c @@ -0,0 +1,25 @@ +/* PR target/100762 + This was triggering an ICE in mips_expand_vector_init when compiled with + -mmsa -mloongson-mmi. */ + +/* { dg-do compile } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT32_TYPE__ int32_t; +typedef int32_t i32x2 __attribute__((__vector_size__(8))); + +i32x2 cmp(i32x2 a, i32x2 b) { + return a >= b; +} + +i32x2 shift(i32x2 a, i32x2 b) { + return a >> b; +} + +i32x2 mul(i32x2 a, i32x2 b) { + return a * b; +} + +i32x2 div(i32x2 a, i32x2 b) { + return a / b; +}