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a=ed25519-sha256; c=relaxed/relaxed; t=1709901572; s=strato-dkim-0003; d=gjlay.de; h=Subject:To:From:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=ApOSEz/MwhWJbsdWJmeRqqH/It7EEF5yreL9bKuFZuA=; b=0NpIvxkTTaUfGMIz64ayCNS4strhL65gKfmoRAu8OPydKxl0h985gLsUNMA9SzXmJB bZJfKX2kbHeFmFJwAhCA== X-RZG-AUTH: ":LXoWVUeid/7A29J/hMvvT3koxZnKT7Qq0xotTetVnKkSgcSjpmy9KwoMJ/K0VA==" Received: from [192.168.2.102] by smtp.strato.de (RZmta 50.2.0 DYNA|AUTH) with ESMTPSA id xef40c028CdW7K7 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate) for ; Fri, 8 Mar 2024 13:39:32 +0100 (CET) Message-ID: <90e2344f-d4e9-4538-825e-28f23588cb8e@gjlay.de> Date: Fri, 8 Mar 2024 13:39:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Georg-Johann Lay To: "gcc-patches@gcc.gnu.org" Subject: [patch,avr,applied] Add an insn combine pattern for offset computation. X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Computing uint16_t += 2 * uint8_t can occur when an offset into a 16-bit array is computed. Without this pattern is costs six instructions: A move (1), a zero-extend (1), a shift (2) and an addition (2). With this pattern it costs 4. Johann --- AVR: Add an insn combine pattern for offset computation. Computing uint16_t += 2 * uint8_t can occur when an offset into a 16-bit array is computed. Without this pattern is costs six instructions: A move (1), a zero-extend (1), a shift (2) and an addition (2). With this pattern it costs 4. gcc/ * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern. * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost. diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index b87ae6a256d..1fa4b557f5d 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -12513,6 +12513,17 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, return true; case PLUS: + // uint16_t += 2 * uint8_t; + if (mode == HImode + && GET_CODE (XEXP (x, 0)) == ASHIFT + && REG_P (XEXP (x, 1)) + && XEXP (XEXP (x, 0), 1) == const1_rtx + && GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) + { + *total = COSTS_N_INSNS (4); + return true; + } + if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND && REG_P (XEXP (x, 1))) { diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index bc8a59c956c..52b6cff4a8b 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -1630,6 +1630,39 @@ (define_insn "*addhi3_zero_extend.const" "subi %A0,%n2\;sbc %B0,%B0" [(set_attr "length" "2")]) + +;; Occurs when computing offsets into 16-bit arrays. +;; Saves up to 2 instructions. +(define_insn_and_split "*addhi3_zero_extend.ashift1.split" + [(set (match_operand:HI 0 "register_operand" "=r") + (plus:HI (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) + (const_int 1)) + (match_operand:HI 2 "register_operand" "0")))] + "" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) + (plus:HI (ashift:HI (zero_extend:HI (match_dup 1)) + (const_int 1)) + (match_dup 2))) + (clobber (reg:CC REG_CC))])]) + +(define_insn "*addhi3_zero_extend.ashift1" + [(set (match_operand:HI 0 "register_operand" "=r") + (plus:HI (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r")) + (const_int 1)) + (match_operand:HI 2 "register_operand" "0"))) + (clobber (reg:CC REG_CC))] + "reload_completed" + { + return reg_overlap_mentioned_p (operands[1], operands[0]) + ? "mov __tmp_reg__,%1\;add %A0,__tmp_reg__\;adc %B0,__zero_reg__\;add %A0,__tmp_reg__\;adc %B0,__zero_reg__" + : "add %A0,%1\;adc %B0,__zero_reg__\;add %A0,%1\;adc %B0,__zero_reg__"; + } + [(set (attr "length") + (symbol_ref ("4 + reg_overlap_mentioned_p (operands[1], operands[0])")))]) + + (define_insn_and_split "*usum_widenqihi3_split" [(set (match_operand:HI 0 "register_operand" "=r") (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))