From patchwork Wed Sep 6 15:14:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 810666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-461618-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="DgzJY8Kz"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xnRwL260qz9t2R for ; Thu, 7 Sep 2017 01:15:14 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:from:to:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=sumqVvgfiX16gusdy Se6sC+79cSZGNx/zCUA7lCj4Bsq1niVzB6+NuVaHLXd91b+fMD60OmL4E9zkJxvP 7l3ISYw8alNAq3NGwm/NP+rpJOIFGB+iNNCEHwVsw4lgnvj8rl6X353NZmmxYaoc FVJAdCYQtyRlMvtUWRD73RF8h4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:from:to:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=bOqn9IqJKgfZpgB+h5yQ1kp ZWXg=; b=DgzJY8KzZcyGLA/A7m1nbALfuxvYGj0XuqSvifLUqaOwSatSmqPCt5I nAC37pI2q9yFh2rLCIlHGQMV6snBKvRx4wyGgkKsUfjawhXFizVaiZ3iYqzElMKE Inp09wUYt6Tsi0BLJ2RjLuQzFeIvBxuEMC+bkCIlvXQq/hlZ+Zag= Received: (qmail 714 invoked by alias); 6 Sep 2017 15:15:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 695 invoked by uid 89); 6 Sep 2017 15:15:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=FLAG, UD:arm.com, STRONG X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Sep 2017 15:14:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1899715AD for ; Wed, 6 Sep 2017 08:14:57 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C20D3F578 for ; Wed, 6 Sep 2017 08:14:56 -0700 (PDT) References: <654b960e-5492-8f51-e125-58e51999eecc@foss.arm.com> Subject: [arm-embedded] [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture From: Thomas Preudhomme To: "gcc-patches@gcc.gnu.org" X-Forwarded-Message-Id: <654b960e-5492-8f51-e125-58e51999eecc@foss.arm.com> Message-ID: <8e2e51bb-31fa-fa69-a32e-0abf0194be1a@foss.arm.com> Date: Wed, 6 Sep 2017 16:14:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <654b960e-5492-8f51-e125-58e51999eecc@foss.arm.com> X-IsSubscribed: yes Hi, We have decided to apply the following patch to the embedded-7-branch to enable ARMv8-R support. ChangeLog entry is as follows: *** gcc/ChangeLog.arm *** 2017-09-04 Thomas Preud'homme Backport from mainline 2017-07-06 Thomas Preud'homme * config/arm/arm-cpus.in (armv8-r): Add new entry. * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R enumerator. * doc/invoke.texi: Mention -march=armv8-r and its extensions. *** gcc/testsuite/ChangeLog *** 2017-09-04 Thomas Preud'homme Backport from mainline 2017-07-06 Thomas Preud'homme * lib/target-supports.exp: Generate check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r and check_effective_target_arm_arch_v8r_multilib. *** libgcc/ChangeLog *** 2017-09-04 Thomas Preud'homme Backport from mainline 2017-07-06 Thomas Preud'homme * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R. Please find an updated patch in attachment. ChangeLog entry are now as follows: *** gcc/ChangeLog *** 2017-07-06 Thomas Preud'homme * config/arm/arm-cpus.in (armv8-r): Add new entry. * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R enumerator. * doc/invoke.texi: Mention -march=armv8-r and its extensions. *** gcc/testsuite/ChangeLog *** 2017-01-31 Thomas Preud'homme * lib/target-supports.exp: Generate check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r and check_effective_target_arm_arch_v8r_multilib. *** libgcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R. Tested by building an arm-none-eabi GCC cross-compiler targetting ARMv8-R. Is this ok for stage1? Best regards, Thomas Best regards, Thomas On 29/06/17 16:13, Thomas Preudhomme wrote: > Please ignore this patch. I'll respin the patch on a more recent GCC. > > Best regards, > > Thomas > > On 29/06/17 14:55, Thomas Preudhomme wrote: >> Hi, >> >> This patch adds support for ARMv8-R architecture [1] which was recently >> announced. User level instructions for ARMv8-R are the same as those in >> ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same >> features as ARMv8-A in ARM backend. >> >> [1] >> https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile >> >> >> ChangeLog entries are as follow: >> >> *** gcc/ChangeLog *** >> >> 2017-01-31 Thomas Preud'homme >> >> * config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry. >> * config/arm/arm-cpu-cdata.h: Regenerate. >> * config/arm/arm-cpu-data.h: Regenerate. >> * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. >> * config/arm/arm-tables.opt: Regenerate. >> * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R >> enumerator. >> * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and >> ARMv8-R with CRC extensions. >> * doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc >> options. Document meaning of -march=armv8-r+rcr. >> >> *** gcc/testsuite/ChangeLog *** >> >> 2017-01-31 Thomas Preud'homme >> >> * lib/target-supports.exp: Generate >> check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r >> and check_effective_target_arm_arch_v8r_multilib. >> >> *** libgcc/ChangeLog *** >> >> 2017-01-31 Thomas Preud'homme >> >> * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R. >> >> Tested by building an arm-none-eabi GCC cross-compiler targetting >> ARMv8-R. >> >> Is this ok for stage1? >> >> Best regards, >> >> Thomas diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 946d543ebb29416da9b4928161607cccacaa78a7..f35128acb7d68c6a0592355b9d3d56ee8f826aca 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -380,6 +380,22 @@ begin arch armv8-m.main option nodsp remove bit_ARMv7em end arch armv8-m.main +begin arch armv8-r + tune for cortex-r4 + tune flags CO_PROC + base 8R + profile R + isa ARMv8r + option crc add bit_crc32 +# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision +# note: no fp option for fp-armv8 (d16) + double precision at the moment + option fp.sp add FP_ARMv8 + option simd add FP_ARMv8 NEON + option crypto add FP_ARMv8 CRYPTO + option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP +end arch armv8-r + begin arch iwmmxt tune for iwmmxt tune flags LDSCHED STRONG XSCALE diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index c0c2ccee330f2313951e980c5d399ae5d21005d6..0d66a0400c517668db023fc66ff43e26d43add51 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -127,6 +127,7 @@ enum isa_feature #define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse +#define ISA_ARMv8r ISA_ARMv8a /* List of all cryptographic extensions to stripout if crypto is disabled. Currently, that's trivial, but we define it anyway for diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 5e2df9dd0716293fb551b6582a8c9c2c46fdaa90..51678c2566e841894c5c0e9c613c8c0f832e9988 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -455,10 +455,13 @@ EnumValue Enum(arm_arch) String(armv8-m.main) Value(30) EnumValue -Enum(arm_arch) String(iwmmxt) Value(31) +Enum(arm_arch) String(armv8-r) Value(31) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(32) +Enum(arm_arch) String(iwmmxt) Value(32) + +EnumValue +Enum(arm_arch) String(iwmmxt2) Value(33) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index c803d4461c08436ef5f8468f6018e3226ccf33f8..315622212a5ce10d0c771535fe31f63c3be16444 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -384,7 +384,8 @@ enum base_architecture BASE_ARCH_7EM = 7, BASE_ARCH_8A = 8, BASE_ARCH_8M_BASE = 8, - BASE_ARCH_8M_MAIN = 8 + BASE_ARCH_8M_MAIN = 8, + BASE_ARCH_8R = 8 }; /* The major revision number of the ARM Architecture implemented by the target. */ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3e5cee8649ef9452e2a7e5a8603318ce11e2baff..d0b90503cedaae32bc83c7fd1fdd78b2a4d7184b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15218,6 +15218,7 @@ Permissible names are: @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv7-r}, +@samp{armv8-r}, @samp{armv6-m}, @samp{armv6s-m}, @samp{armv7-m}, @samp{armv7e-m}, @samp{armv8-m.base}, @samp{armv8-m.main}, @@ -15484,7 +15485,20 @@ The single- and double-precision floating-point instructions. @item +nofp Disable the floating-point extension. +@end table +@item armv8-r +@table @samp +@item +crc +The Cyclic Redundancy Check (CRC) instructions. +@item +simd +The ARMv8 Advanced SIMD and floating-point instructions. +@item +crypto +The cryptographic instructions. +@item +nocrypto +Disable the cryptographic isntructions. +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. @end table @end table diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fe5e77756404d603f04d674bb5ca872956d4b7ad..83d0c7ca441570dbf4d52641d12073f17d06e025 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3890,7 +3890,8 @@ foreach { armfunc armflag armdefs } { v8_2a "-march=armv8.2a" __ARM_ARCH_8A__ v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft" __ARM_ARCH_8M_BASE__ - v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } { + v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ + v8r "-march=armv8-r" __ARM_ARCH_8R__ } { eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] { proc check_effective_target_arm_arch_FUNC_ok { } { if { [ string match "*-marm*" "FLAG" ] && diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #endif #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) + || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) # define __ARM_ARCH__ 8 #endif