From patchwork Fri Nov 22 08:31:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 293370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A687F2C0141 for ; Fri, 22 Nov 2013 19:32:19 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=hymeBXsysdBj5xEXorATwoQ+fjsTfi6/Dkx4f0WYOTjxDWJZGM ktTlGpgQt6QXMTmtP3aGJwI64eqyHUAIOPzIsSY45SgmjsD2qDfGfsjquFTich2k FSD60A6/207r7DqTF07b4S1vfAgdc75S/4J4zwmAnNHlux5hgN12BhzNI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=teILe3R9yNFhDz1zWT3ESszdCaE=; b=ORo925zBplOli0+Tj3vp ucczJ6uY5LHlxrYKNzGOkGgFh/ql9zmi2MXBNEf/b5O/fqKTFPM4IzJr9JYZSXcB RNtRM7bWd17ULipMiLfobzptgRrY9eO6x6Hv4QNYujLi8gHL9ZMgil0QyHkASDlB 1AuicbXn1ihPqnzOWg3tFpE= Received: (qmail 20527 invoked by alias); 22 Nov 2013 08:32:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20501 invoked by uid 89); 22 Nov 2013 08:32:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.1 required=5.0 tests=AWL, BAYES_40, FREEMAIL_FROM, RDNS_NONE, SPF_PASS, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mail-wi0-f175.google.com Received: from Unknown (HELO mail-wi0-f175.google.com) (209.85.212.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 22 Nov 2013 08:31:14 +0000 Received: by mail-wi0-f175.google.com with SMTP id hi5so363921wib.14 for ; Fri, 22 Nov 2013 00:31:05 -0800 (PST) X-Received: by 10.194.21.131 with SMTP id v3mr825389wje.44.1385109065539; Fri, 22 Nov 2013 00:31:05 -0800 (PST) Received: from localhost ([2.28.235.51]) by mx.google.com with ESMTPSA id bk7sm13687881wib.10.2013.11.22.00.31.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Nov 2013 00:31:05 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, walt@tilera.com, rdsandiford@googlemail.com Cc: walt@tilera.com Subject: [tilegx] Avoid genrecog warning Date: Fri, 22 Nov 2013 08:31:04 +0000 Message-ID: <87wqk04z3r.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 I have a patch to upgrade most genrecog warnings into errors. This patch fixes those for tilegx. There seemed to be two sources of warnings: - the intrinsics often used matched pointer_operands in an addition, so that the destination accepted constant pointers. I think the direct translation would be pmode_register_operand, but since these additions have a specific mode, I think a modeful register_operand is more natural. - some instructions used reg_or_0_operand as a destination. Tested by building tilegx-elf with the warnings turned to errors, and by comparing the before and after assembly output at -O2 for gcc.c-torture, gcc.dg and g++.dg. OK to install? Thanks, Richard gcc/ * config/tilegx/tilegx.md (insn_ld_add): Use register_operand rather than pointer_operand. Add modes to the operands. (insn_ldna_add): Likewise. (insn_ld_add): Likewise. (insn_ldnt_add): Likewise. (insn_ldnt_add): Likewise. (insn_ld_add_L2): Likewise. (insn_ldna_add_L2): Likewise. (insn_ld_add_L2): Likewise. (insn_ldnt_add_L2): Likewise. (insn_ldnt_add_L2): Likewise. (insn_ld_add_miss): Likewise. (insn_ldna_add_miss): Likewise. (insn_ld_add_miss): Likewise. (insn_ldnt_add_miss): Likewise. (insn_ldnt_add_miss): Likewise. (insn_st_add): Likewise. (insn_st_add): Likewise. (*insn_st_add): Likewise. (insn_stnt_add): Likewise. (insn_stnt_add): Likewise. (*insn_stnt_add): Likewise. (vec_pack__v4hi): Use register_operand rather than reg_or_0_operand for operand 0. (insn_v2): Likewise. (vec_pack_hipart_v4hi): Likewise. (insn_v2packh): Likewise. (vec_pack_ssat_v2si): Likewise. (insn_v4packsc): Likewise. Index: gcc/config/tilegx/tilegx.md =================================================================== --- gcc/config/tilegx/tilegx.md 2013-11-16 21:52:15.083787117 +0000 +++ gcc/config/tilegx/tilegx.md 2013-11-16 21:59:07.745113525 +0000 @@ -3284,9 +3284,9 @@ (define_expand "insn_ld" "") (define_insn "insn_ld_add" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (mem:DI (match_dup 3)))] "" @@ -3302,9 +3302,9 @@ (define_insn "insn_ldna" [(set_attr "type" "X1_2cycle")]) (define_insn "insn_ldna_add" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (mem:DI (and:DI (match_dup 3) (const_int -8))))] "" @@ -3318,9 +3318,9 @@ (define_expand "insn_ld" "") (define_insn "insn_ld_add" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI (mem:I124MODE (match_dup 3))))] "" @@ -3338,9 +3338,9 @@ (define_insn "insn_ldnt" [(set_attr "type" "X1_2cycle")]) (define_insn "insn_ldnt_add" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(mem:DI (match_dup 3))] UNSPEC_NON_TEMPORAL))] @@ -3359,9 +3359,9 @@ (define_insn "insn_ldnt" [(set_attr "type" "X1_2cycle")]) (define_insn "insn_ldnt_add" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))] UNSPEC_NON_TEMPORAL)))] @@ -3380,9 +3380,9 @@ (define_insn "insn_ld_L2" [(set_attr "type" "Y2_L2")]) (define_insn "insn_ld_add_L2" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(mem:DI (match_dup 3))] UNSPEC_LATENCY_L2))] @@ -3400,9 +3400,9 @@ (define_insn "insn_ldna_L2" [(set_attr "type" "X1_L2")]) (define_insn "insn_ldna_add_L2" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))] UNSPEC_LATENCY_L2))] @@ -3421,9 +3421,9 @@ (define_insn "insn_ld_L2" [(set_attr "type" "Y2_L2")]) (define_insn "insn_ld_add_L2" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))] UNSPEC_LATENCY_L2)))] @@ -3444,9 +3444,9 @@ (define_insn "insn_ldnt_L2" [(set_attr "type" "X1_L2")]) (define_insn "insn_ldnt_add_L2" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(unspec:DI [(mem:DI (match_dup 3))] @@ -3469,9 +3469,9 @@ (define_insn "insn_ldnt_L2" [(set_attr "type" "X1_L2")]) (define_insn "insn_ldnt_add_L2" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI (unspec:I124MODE [(unspec:I124MODE @@ -3493,9 +3493,9 @@ (define_insn "insn_ld_miss" [(set_attr "type" "Y2_miss")]) (define_insn "insn_ld_add_miss" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(mem:DI (match_dup 3))] UNSPEC_LATENCY_MISS))] @@ -3513,9 +3513,9 @@ (define_insn "insn_ldna_miss" [(set_attr "type" "X1_miss")]) (define_insn "insn_ldna_add_miss" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))] UNSPEC_LATENCY_MISS))] @@ -3534,9 +3534,9 @@ (define_insn "insn_ld_miss" [(set_attr "type" "Y2_miss")]) (define_insn "insn_ld_add_miss" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))] UNSPEC_LATENCY_MISS)))] @@ -3557,9 +3557,9 @@ (define_insn "insn_ldnt_miss" [(set_attr "type" "X1_miss")]) (define_insn "insn_ldnt_add_miss" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(unspec:DI [(mem:DI (match_dup 3))] @@ -3582,9 +3582,9 @@ (define_insn "insn_ldnt_miss" [(set_attr "type" "X1_miss")]) (define_insn "insn_ldnt_add_miss" - [(set (match_operand:I48MODE 1 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "1") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 1 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI (unspec:I124MODE [(unspec:I124MODE @@ -3969,9 +3969,9 @@ (define_expand "insn_st" "") (define_insn "insn_st_add" - [(set (match_operand:I48MODE 0 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "0") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 0 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (mem:DI (match_dup 3)) (match_operand:DI 1 "reg_or_0_operand" "rO"))] "" @@ -3988,9 +3988,9 @@ (define_expand "insn_st" (define_expand "insn_st_add" [(parallel - [(set (match_operand:I48MODE 0 "pointer_operand" "") - (plus:I48MODE (match_operand 3 "pointer_operand" "") - (match_operand 2 "s8bit_cint_operand" ""))) + [(set (match_operand:I48MODE 0 "register_operand" "") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "") + (match_operand:I48MODE 2 "s8bit_cint_operand" ""))) (set (mem:I124MODE (match_dup 3)) (match_operand:DI 1 "reg_or_0_operand" ""))])] "" @@ -4000,9 +4000,9 @@ (define_expand "insn_st_add< }) (define_insn "*insn_st_add" - [(set (match_operand:I48MODE 0 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "0") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 0 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (mem:I124MODE (match_dup 3)) (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))] "" @@ -4020,9 +4020,9 @@ (define_insn "insn_stnt" [(set_attr "type" "X1")]) (define_insn "insn_stnt_add" - [(set (match_operand:I48MODE 0 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "0") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 0 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (mem:DI (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL)) (match_operand:DI 1 "reg_or_0_operand" "rO"))] "" @@ -4048,9 +4048,9 @@ (define_insn "*insn_stnt" (define_expand "insn_stnt_add" [(parallel - [(set (match_operand:I48MODE 0 "pointer_operand" "") - (plus:I48MODE (match_operand 3 "pointer_operand" "") - (match_operand 2 "s8bit_cint_operand" ""))) + [(set (match_operand:I48MODE 0 "register_operand" "") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "") + (match_operand:I48MODE 2 "s8bit_cint_operand" ""))) (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL)) (match_operand:DI 1 "reg_or_0_operand" "rO"))])] "" @@ -4060,9 +4060,9 @@ (define_expand "insn_stnt_ad }) (define_insn "*insn_stnt_add" - [(set (match_operand:I48MODE 0 "pointer_operand" "=r") - (plus:I48MODE (match_operand 3 "pointer_operand" "0") - (match_operand 2 "s8bit_cint_operand" "i"))) + [(set (match_operand:I48MODE 0 "register_operand" "=r") + (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0") + (match_operand:I48MODE 2 "s8bit_cint_operand" "i"))) (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL)) (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))] "" @@ -4828,7 +4828,7 @@ (define_expand "insn_v2muls" ;; {B3,B2,B1,B0} {A3,A2,A1,A0} ;; => {A3,A2,A1,A0,B3,B2,B1,B0} (define_insn "vec_pack__v4hi" - [(set (match_operand:V8QI 0 "reg_or_0_operand" "=r") + [(set (match_operand:V8QI 0 "register_operand" "=r") (vec_concat:V8QI (v2pack:V4QI (match_operand:V4HI 1 "reg_or_0_operand" "rO")) (v2pack:V4QI (match_operand:V4HI 2 "reg_or_0_operand" "rO"))))] @@ -4837,7 +4837,7 @@ (define_insn "vec_pack__v4hi [(set_attr "type" "X01")]) (define_expand "insn_v2" - [(set (match_operand:DI 0 "reg_or_0_operand" "") + [(set (match_operand:DI 0 "register_operand" "") (vec_concat:V8QI (v2pack:V4QI (match_operand:DI 2 "reg_or_0_operand" "")) (v2pack:V4QI (match_operand:DI 1 "reg_or_0_operand" ""))))] @@ -4855,7 +4855,7 @@ (define_expand "insn_v2" ;; {B3,B2,B1,B0} {A3,A2,A1,A0} ;; => {A3_hi,A2_hi,A1_hi,A0_hi,B3_hi,B2_hi,B1_hi,B0_hi} (define_insn "vec_pack_hipart_v4hi" - [(set (match_operand:V8QI 0 "reg_or_0_operand" "=r") + [(set (match_operand:V8QI 0 "register_operand" "=r") (vec_concat:V8QI (truncate:V4QI (ashiftrt:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rO") @@ -4868,7 +4868,7 @@ (define_insn "vec_pack_hipart_v4hi" [(set_attr "type" "X01")]) (define_expand "insn_v2packh" - [(set (match_operand:DI 0 "reg_or_0_operand" "") + [(set (match_operand:DI 0 "register_operand" "") (vec_concat:V8QI (truncate:V4QI (ashiftrt:V4HI (match_operand:DI 2 "reg_or_0_operand" "") @@ -4890,7 +4890,7 @@ (define_expand "insn_v2packh" ;; {B1,B0} {A1,A0} ;; => {A1,A0,B1,B0} (define_insn "vec_pack_ssat_v2si" - [(set (match_operand:V4HI 0 "reg_or_0_operand" "=r") + [(set (match_operand:V4HI 0 "register_operand" "=r") (vec_concat:V4HI (us_truncate:V2HI (match_operand:V2SI 1 "reg_or_0_operand" "rO")) (us_truncate:V2HI (match_operand:V2SI 2 "reg_or_0_operand" "rO"))))] @@ -4899,7 +4899,7 @@ (define_insn "vec_pack_ssat_v2si" [(set_attr "type" "X01")]) (define_expand "insn_v4packsc" - [(set (match_operand:DI 0 "reg_or_0_operand" "") + [(set (match_operand:DI 0 "register_operand" "") (vec_concat:V4HI (us_truncate:V2HI (match_operand:DI 2 "reg_or_0_operand" "")) (us_truncate:V2HI (match_operand:DI 1 "reg_or_0_operand" ""))))]