From patchwork Sun Feb 2 16:19:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 316010 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D68A42C0091 for ; Mon, 3 Feb 2014 03:20:05 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=jYffbH55LNQpY3FsW2R+wRXvg9LKe6SQThkyqGRGdZhoXPt+xlPYq yxUSeIlmU3Ge/xgjLtZR+ESjaCQmSltKByhKEh/K1UQwgyeiQNJhMwHmd9H5hvcL qCjzmFnuEEtmFJG9igwsbnFfoN3LP7SoWkMnPPzOmomJJFIP7Q/jmc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=M5FwsBmhMDb5oWp6Smu55RcxFQI=; b=Uym/IgWwzUOe8ED0FaY0 cQ94U26CqQ++8dxIdAA1myYYI3y203DssALijfrQdayePZrIT94Wd8ax65bzzhMu VJq7tI4x1PGS2ROa9WpHp2h0fTaG0lzQha5EwUU0OkJlYKnS4Ksdg1d+m37odwKc Igu56Pd/ZNKXr4Ms+AbpXUA= Received: (qmail 18694 invoked by alias); 2 Feb 2014 16:19:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18682 invoked by uid 89); 2 Feb 2014 16:19:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=3.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, KAM_STOCKTIP, RCVD_IN_DNSWL_LOW, SPF_PASS, URIBL_BLACK autolearn=no version=3.3.2 X-HELO: mail-wg0-f50.google.com Received: from mail-wg0-f50.google.com (HELO mail-wg0-f50.google.com) (74.125.82.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sun, 02 Feb 2014 16:19:54 +0000 Received: by mail-wg0-f50.google.com with SMTP id l18so11032096wgh.29 for ; Sun, 02 Feb 2014 08:19:50 -0800 (PST) X-Received: by 10.194.57.239 with SMTP id l15mr1431775wjq.40.1391357990807; Sun, 02 Feb 2014 08:19:50 -0800 (PST) Received: from localhost ([2.28.234.162]) by mx.google.com with ESMTPSA id jc5sm13672488wic.10.2014.02.02.08.19.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Feb 2014 08:19:50 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com Subject: [MIPS] Use soft-fp for libgcc floating-point routines Date: Sun, 02 Feb 2014 16:19:44 +0000 Message-ID: <87vbwx8p27.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 This patch (finally!) moves MIPS over to the soft-fp routines. The main advantage is that we now handle 128-bit long-double exceptions properly on hard-float targets. This also removes the last use of TPBIT in libgcc. It might be worth removing support for that at some point -- including the associated libgcc2.c routines -- but probably not at this stage of 4.9. Tested on mips64-linux-gnu and mipsisa64-sde-elf. It fixes the c11-atomic-exec-5.c failures for n32 and n64. I also checked that the exported libgcc.so symbols were unchanged for all 3 GNU/Linux ABIs, just to be sure. I also did some spot checking of FCSR values after long-double operations, as well as checking that SIGFPE was raised for long-double operations when the associated enable bit was set. Applied. Thanks, Richard libgcc/ * configure.ac: Check __mips64 when setting host_address. * configure: Regenerate. * config.host (mips*-*-*): Add t-softfp-sfdf, mips/t-softfp-tf, mips/t-mips64 and t-softfp. (mips*-*-linux*): Don't add mips/t-tpbit. * config/mips/t-mips (LIB2_SIDITI_CONV_FUNCS, FPBIT, FPBIT_CFLAGS) (DPBIT, DPBIT_CFLAGS): Delete. * config/mips/sfp-machine.h: New file. * config/mips/t-mips64: Likewise. * config/mips/t-softfp-tf: Likewise. * config/mips/t-tpbit: Delete. Index: libgcc/configure.ac =================================================================== --- libgcc/configure.ac 2014-02-02 08:29:06.963467177 +0000 +++ libgcc/configure.ac 2014-02-02 08:37:35.158153333 +0000 @@ -279,9 +279,11 @@ AC_CACHE_CHECK([whether assembler suppor [libgcc_cv_cfi=yes], [libgcc_cv_cfi=no])]) -# Check 32bit or 64bit +# Check 32bit or 64bit. In the case of MIPS, this really determines the +# word size rather than the address size. cat > conftest.c <. */ + +#ifdef __mips64 +#define _FP_W_TYPE_SIZE 64 +#define _FP_W_TYPE unsigned long long +#define _FP_WS_TYPE signed long long +#define _FP_I_TYPE long long + +typedef int TItype __attribute__ ((mode (TI))); +typedef unsigned int UTItype __attribute__ ((mode (TI))); +#define TI_BITS (__CHAR_BIT__ * (int) sizeof (TItype)) + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) + +#ifdef __mips_nan2008 +# define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +# define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) +# define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 +#else +# define _FP_NANFRAC_S (_FP_QNANBIT_S - 1) +# define _FP_NANFRAC_D (_FP_QNANBIT_D - 1) +# define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1 +#endif +#else +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned int +#define _FP_WS_TYPE signed int +#define _FP_I_TYPE int + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) + +#ifdef __mips_nan2008 +# define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +# define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 +# define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 +#else +# define _FP_NANFRAC_S (_FP_QNANBIT_S - 1) +# define _FP_NANFRAC_D (_FP_QNANBIT_D - 1), -1 +# define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1, -1, -1 +#endif +#endif + +/* The type of the result of a floating point comparison. This must + match __libgcc_cmp_return__ in GCC for the target. */ +typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); +#define CMPtype __gcc_CMPtype + +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_NANSIGN_Q 0 + +#define _FP_KEEPNANFRACP 1 +#ifdef __mips_nan2008 +# define _FP_QNANNEGATEDP 0 +#else +# define _FP_QNANNEGATEDP 1 +#endif + +/* Comment from glibc: */ +/* From my experiments it seems X is chosen unless one of the + NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do { \ + if ((_FP_FRAC_HIGH_RAW_##fs(X) | \ + _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \ + { \ + R##_s = _FP_NANSIGN_##fs; \ + _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \ + } \ + else \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc(R,X); \ + } \ + R##_c = FP_CLS_NAN; \ + } while (0) + +#ifdef __mips_hard_float +#define FP_EX_INVALID 0x40 +#define FP_EX_DIVZERO 0x20 +#define FP_EX_OVERFLOW 0x10 +#define FP_EX_UNDERFLOW 0x08 +#define FP_EX_INEXACT 0x04 +#define FP_EX_ALL \ + (FP_EX_INVALID | FP_EX_DIVZERO | FP_EX_OVERFLOW | FP_EX_UNDERFLOW \ + | FP_EX_INEXACT) + +#define FP_EX_ENABLE_SHIFT 5 +#define FP_EX_CAUSE_SHIFT 10 + +#define FP_RND_NEAREST 0x0 +#define FP_RND_ZERO 0x1 +#define FP_RND_PINF 0x2 +#define FP_RND_MINF 0x3 +#define FP_RND_MASK 0x3 + +#define _FP_DECL_EX \ + unsigned long int _fcsr __attribute__ ((unused)) = FP_RND_NEAREST + +#define FP_INIT_ROUNDMODE \ + do { \ + _fcsr = __builtin_mips_get_fcsr (); \ + } while (0) + +#define FP_ROUNDMODE (_fcsr & FP_RND_MASK) + +#define FP_TRAPPING_EXCEPTIONS ((_fcsr >> FP_EX_ENABLE_SHIFT) & FP_EX_ALL) + +#define FP_HANDLE_EXCEPTIONS \ + do { \ + _fcsr &= ~(FP_EX_ALL << FP_EX_CAUSE_SHIFT); \ + /* Also clear Unimplemented Operation. */ \ + _fcsr &= ~(1 << 17); \ + _fcsr |= _fex | (_fex << FP_EX_CAUSE_SHIFT); \ + __builtin_mips_set_fcsr (_fcsr); \ + } while (0); + +#else +#define FP_EX_INVALID (1 << 4) +#define FP_EX_DIVZERO (1 << 3) +#define FP_EX_OVERFLOW (1 << 2) +#define FP_EX_UNDERFLOW (1 << 1) +#define FP_EX_INEXACT (1 << 0) +#endif + +#define __LITTLE_ENDIAN 1234 +#define __BIG_ENDIAN 4321 + +#if defined _MIPSEB +# define __BYTE_ORDER __BIG_ENDIAN +#else +# define __BYTE_ORDER __LITTLE_ENDIAN +#endif + +/* Define ALIASNAME as a strong alias for NAME. */ +# define strong_alias(name, aliasname) _strong_alias(name, aliasname) +# define _strong_alias(name, aliasname) \ + extern __typeof (name) aliasname __attribute__ ((alias (#name))); Index: libgcc/config/mips/t-mips64 =================================================================== --- /dev/null 2014-01-30 08:06:21.701666182 +0000 +++ libgcc/config/mips/t-mips64 2014-02-02 08:37:35.139153157 +0000 @@ -0,0 +1,1 @@ +softfp_int_modes += ti Index: libgcc/config/mips/t-softfp-tf =================================================================== --- /dev/null 2014-01-30 08:06:21.701666182 +0000 +++ libgcc/config/mips/t-softfp-tf 2014-02-02 08:37:35.139153157 +0000 @@ -0,0 +1,3 @@ +softfp_float_modes += tf +softfp_extensions += sftf dftf +softfp_truncations += tfsf tfdf Index: libgcc/config/mips/t-tpbit =================================================================== --- libgcc/config/mips/t-tpbit 2014-02-02 08:29:06.963467177 +0000 +++ /dev/null 2014-01-30 08:06:21.701666182 +0000 @@ -1,4 +0,0 @@ -ifeq ($(long_double_type_size),128) -TPBIT = true -TPBIT_CFLAGS = -DQUIET_NAN_NEGATED -endif