From patchwork Thu Jan 9 20:06:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 308948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A49A42C00AA for ; Fri, 10 Jan 2014 07:29:04 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=qbuw2iU2EAer9sp3GBweM/wwC4eHSDggt5nHCeB76OF9+ioDwbhQ7 grMTd5Z5hQsMlt7RJTY4OxUcqBtqi5NxqqKAU+NMiY1MWK3oisVzShzL929bfCLH GZd+fhSXmUf8cby//lknAT52HbkB3QI1vxzNJdNORrUM0kyGMaOG3o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=wDkHosB8joE8gMij3MXd+Crwpxw=; b=peDE07Ar5kt3gKgiwbPC OYENbiySeiFwtH321XgZPZa12RlevBX6A9hTwoWmY6nDJ8mYfA4qPzH4QNCTMkZV VJ9kyVE5Ecra8JVfUfC51dlvBz3oYHUVpZRHhpgBLUZK0aJ1J3CN0OACWABISae1 hsg/lsQmaCGxuqw68AZCNp0= Received: (qmail 19638 invoked by alias); 9 Jan 2014 20:27:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22611 invoked by uid 89); 9 Jan 2014 20:06:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f171.google.com Received: from mail-wi0-f171.google.com (HELO mail-wi0-f171.google.com) (209.85.212.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 09 Jan 2014 20:06:37 +0000 Received: by mail-wi0-f171.google.com with SMTP id bz8so7441969wib.16 for ; Thu, 09 Jan 2014 12:06:33 -0800 (PST) X-Received: by 10.180.104.42 with SMTP id gb10mr28095533wib.51.1389297993867; Thu, 09 Jan 2014 12:06:33 -0800 (PST) Received: from localhost ([2.28.234.162]) by mx.google.com with ESMTPSA id pk8sm978416wic.6.2014.01.09.12.06.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jan 2014 12:06:33 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com Subject: [MIPS, committed] Backport bswap patches to 4.8 Date: Thu, 09 Jan 2014 20:06:32 +0000 Message-ID: <87lhyorkc7.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 I got an off-list request to backport the bswap patterns to 4.8. They've been in trunk for a while without any problems being reported and they should be relatively safe. Here's what I applied after testing on mips64-linux-gnu (with --with-arch=mips64r2). The only difference is the use of: [(set_attr "length" "8")] rather than trunk's: [(set_attr "insn_count" "2")] Thanks, Richard gcc/ * config/mips/mips.h (ISA_HAS_WSBH): Define. * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New constants. (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns. gcc/testsuite/ * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c, gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c, gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests. Index: gcc/config/mips/mips.h =================================================================== --- gcc/config/mips/mips.h 2014-01-09 14:59:58.086893612 +0000 +++ gcc/config/mips/mips.h 2014-01-09 15:01:20.065606374 +0000 @@ -949,6 +949,11 @@ #define ISA_HAS_ROR ((ISA_MIPS32R2 \ || TARGET_SMARTMIPS) \ && !TARGET_MIPS16) +/* ISA has the WSBH (word swap bytes within halfwords) instruction. + 64-bit targets also provide DSBH and DSHD. */ +#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \ + && !TARGET_MIPS16) + /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || TARGET_LOONGSON_2EF \ Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md 2014-01-09 15:01:08.387504683 +0000 +++ gcc/config/mips/mips.md 2014-01-09 15:02:06.590011975 +0000 @@ -73,6 +73,11 @@ (define_c_enum "unspec" [ UNSPEC_STORE_LEFT UNSPEC_STORE_RIGHT + ;; Integer operations that are too cumbersome to describe directly. + UNSPEC_WSBH + UNSPEC_DSBH + UNSPEC_DSHD + ;; Floating-point moves. UNSPEC_LOAD_LOW UNSPEC_LOAD_HIGH @@ -5379,6 +5384,56 @@ (define_insn "rotr3" } [(set_attr "type" "shift") (set_attr "mode" "")]) + +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "register_operand" "d")))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn_and_split "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "ISA_HAS_WSBH && ISA_HAS_ROR" + "#" + "" + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) + (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] + "" + [(set_attr "length" "8")]) + +(define_insn_and_split "bswapdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (bswap:DI (match_operand:DI 1 "register_operand" "d")))] + "TARGET_64BIT && ISA_HAS_WSBH" + "#" + "" + [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) + (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] + "" + [(set_attr "length" "8")]) + +(define_insn "wsbh" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dsbh" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dshd" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dshd\t%0,%1" + [(set_attr "type" "shift")]) ;; ;; .................... Index: gcc/testsuite/gcc.target/mips/bswap-1.c =================================================================== --- /dev/null 2013-12-26 20:29:50.272541227 +0000 +++ gcc/testsuite/gcc.target/mips/bswap-1.c 2014-01-09 15:01:20.067606391 +0000 @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return ((x << 8) & 0xff00) | ((x >> 8) & 0xff); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ Index: gcc/testsuite/gcc.target/mips/bswap-2.c =================================================================== --- /dev/null 2013-12-26 20:29:50.272541227 +0000 +++ gcc/testsuite/gcc.target/mips/bswap-2.c 2014-01-09 15:01:20.067606391 +0000 @@ -0,0 +1,9 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return __builtin_bswap16 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ Index: gcc/testsuite/gcc.target/mips/bswap-3.c =================================================================== --- /dev/null 2013-12-26 20:29:50.272541227 +0000 +++ gcc/testsuite/gcc.target/mips/bswap-3.c 2014-01-09 15:01:20.067606391 +0000 @@ -0,0 +1,14 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return (((x << 24) & 0xff000000) + | ((x << 8) & 0xff0000) + | ((x >> 8) & 0xff00) + | ((x >> 24) & 0xff)); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ Index: gcc/testsuite/gcc.target/mips/bswap-4.c =================================================================== --- /dev/null 2013-12-26 20:29:50.272541227 +0000 +++ gcc/testsuite/gcc.target/mips/bswap-4.c 2014-01-09 15:01:20.068606400 +0000 @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ Index: gcc/testsuite/gcc.target/mips/bswap-5.c =================================================================== --- /dev/null 2013-12-26 20:29:50.272541227 +0000 +++ gcc/testsuite/gcc.target/mips/bswap-5.c 2014-01-09 15:01:20.068606400 +0000 @@ -0,0 +1,20 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return (((x << 56) & 0xff00000000000000ull) + | ((x << 40) & 0xff000000000000ull) + | ((x << 24) & 0xff0000000000ull) + | ((x << 8) & 0xff00000000ull) + | ((x >> 8) & 0xff000000) + | ((x >> 24) & 0xff0000) + | ((x >> 40) & 0xff00) + | ((x >> 56) & 0xff)); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ Index: gcc/testsuite/gcc.target/mips/bswap-6.c =================================================================== --- /dev/null 2013-12-26 20:29:50.272541227 +0000 +++ gcc/testsuite/gcc.target/mips/bswap-6.c 2014-01-09 15:01:20.068606400 +0000 @@ -0,0 +1,12 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */