From patchwork Wed Jan 8 19:33:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 308413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44DE62C00B8 for ; Thu, 9 Jan 2014 06:33:14 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=NFY6hwRDxUdzGhazxu+DDDf4mTVWLfZra5gmo1Yx6SaE1BdH+6/dc kIBbnj+6QJobaK+Aa6EkNIRULLyJruA3VL0XWXaifhDoi3bTzFK9naOvxUC8pEit pVtb/4+kpc9Hdb8g6SRwAsYzLYOXzrAPIU39Qip/CCxKxZXQHlnJZ8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=QRnxGyfWuQtnaZHsfa5ujvfvWMI=; b=Bek83W6RCxSmffRMw35Y u7h9ngJFYMl36a2H6Ru0xZCd6DLGiVBa2seMlRyruOCB9+ardV8NpTP4qj30TIeR pot/7kA+k7bMqg2Fq1Nv5wYKY+PssVSM3mm+BszB1UMxln/yqDvQSWXZvwcRkPn9 UNNcC+PYElZoZWruFecVJ24= Received: (qmail 30697 invoked by alias); 8 Jan 2014 19:33:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30688 invoked by uid 89); 8 Jan 2014 19:33:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f176.google.com Received: from mail-wi0-f176.google.com (HELO mail-wi0-f176.google.com) (209.85.212.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 08 Jan 2014 19:33:05 +0000 Received: by mail-wi0-f176.google.com with SMTP id hq4so6003000wib.15 for ; Wed, 08 Jan 2014 11:33:02 -0800 (PST) X-Received: by 10.180.14.195 with SMTP id r3mr22841569wic.51.1389209582640; Wed, 08 Jan 2014 11:33:02 -0800 (PST) Received: from localhost ([2.28.234.162]) by mx.google.com with ESMTPSA id k10sm18945562wjf.11.2014.01.08.11.33.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Jan 2014 11:33:02 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com Subject: [MIPS, committed] Revert some Octeon BADDU patches Date: Wed, 08 Jan 2014 19:33:01 +0000 Message-ID: <878uuqtgk2.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 This patch just reverts some changes I'd made to the BADDU patterns for the infamous (truncate:QI (plus:SI ...)) -> (plus:QI ...) simplification. That simplification was limited to CISCy targets for PR 58295. Tested on mips64-linux-gnu and applied. It fixes the octeon-baddu-1.c failures. Thanks, Richard gcc/ Revert: 2012-10-07 Richard Sandiford * config/mips/mips.c (mips_truncated_op_cost): New function. (mips_rtx_costs): Adjust test for BADDU. * config/mips/mips.md (*baddu_di): Push truncates to operands. 2012-10-02 Richard Sandiford * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... (*baddu_si): ...this new pattern. Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2014-01-02 22:16:09.486330453 +0000 +++ gcc/config/mips/mips.c 2014-01-08 10:42:17.727013965 +0000 @@ -3634,17 +3634,6 @@ mips_set_reg_reg_cost (enum machine_mode } } -/* Return the cost of an operand X that can be trucated for free. - SPEED says whether we're optimizing for size or speed. */ - -static int -mips_truncated_op_cost (rtx x, bool speed) -{ - if (GET_CODE (x) == TRUNCATE) - x = XEXP (x, 0); - return set_src_cost (x, speed); -} - /* Implement TARGET_RTX_COSTS. */ static bool @@ -4037,13 +4026,12 @@ mips_rtx_costs (rtx x, int code, int out case ZERO_EXTEND: if (outer_code == SET && ISA_HAS_BADDU + && (GET_CODE (XEXP (x, 0)) == TRUNCATE + || GET_CODE (XEXP (x, 0)) == SUBREG) && GET_MODE (XEXP (x, 0)) == QImode - && GET_CODE (XEXP (x, 0)) == PLUS) + && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) { - rtx plus = XEXP (x, 0); - *total = (COSTS_N_INSNS (1) - + mips_truncated_op_cost (XEXP (plus, 0), speed) - + mips_truncated_op_cost (XEXP (plus, 1), speed)); + *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); return true; } *total = mips_zero_extend_cost (mode, XEXP (x, 0)); Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md 2014-01-08 10:29:42.171963087 +0000 +++ gcc/config/mips/mips.md 2014-01-08 10:38:05.799078793 +0000 @@ -1312,20 +1312,32 @@ (define_insn_and_split "*addsi3_extended ;; Combiner patterns for unsigned byte-add. -(define_insn "*baddu_si" +(define_insn "*baddu_si_eb" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI - (plus:QI (match_operand:QI 1 "register_operand" "d") - (match_operand:QI 2 "register_operand" "d"))))] - "ISA_HAS_BADDU" + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 3)))] + "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" + "baddu\\t%0,%1,%2" + [(set_attr "alu_type" "add")]) + +(define_insn "*baddu_si_el" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 0)))] + "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) (define_insn "*baddu_di" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR - (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d")) - (truncate:QI (match_operand:DI 2 "register_operand" "d")))))] + (truncate:QI + (plus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")])