From patchwork Sat Aug 20 19:02:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 110782 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 4F415B6F7C for ; Sun, 21 Aug 2011 05:03:04 +1000 (EST) Received: (qmail 28934 invoked by alias); 20 Aug 2011 19:03:02 -0000 Received: (qmail 28893 invoked by uid 22791); 20 Aug 2011 19:03:01 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-ww0-f51.google.com (HELO mail-ww0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 20 Aug 2011 19:02:47 +0000 Received: by wwi18 with SMTP id 18so3742430wwi.8 for ; Sat, 20 Aug 2011 12:02:46 -0700 (PDT) Received: by 10.227.162.201 with SMTP id w9mr595860wbx.28.1313866966073; Sat, 20 Aug 2011 12:02:46 -0700 (PDT) Received: from localhost (rsandifo.gotadsl.co.uk [82.133.89.107]) by mx.google.com with ESMTPS id fy12sm3532651wbb.32.2011.08.20.12.02.44 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 20 Aug 2011 12:02:45 -0700 (PDT) From: Richard Sandiford To: Vladimir Makarov Mail-Followup-To: Vladimir Makarov , "gcc-patches\@gcc.gnu.org" , rdsandiford@googlemail.com Cc: "gcc-patches\@gcc.gnu.org" Subject: [MIPS, committed] Fix mips_class_max_nregs References: <4E4EE1A3.7010103@redhat.com> <87liuo5r1n.fsf@firetop.home> Date: Sat, 20 Aug 2011 20:02:43 +0100 In-Reply-To: <87liuo5r1n.fsf@firetop.home> (Richard Sandiford's message of "Sat, 20 Aug 2011 11:13:40 +0100") Message-ID: <877h676h4c.fsf_-_@firetop.home> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.2 (gnu/linux) MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Richard Sandiford writes: > In this case it's a MIPS backend bug. The single pressure class > for MIPS is ALL_REGS, and CLASS_MAX_NREGS (ALL_REGS, TImode) > is returning 4, based on the fact that ALL_REGS includes the > floating-point condition codes. (CCmode is hard-wired to 4 bytes, > so for CCV2 and CCV4, the correct number of registers is the size > of the mode divided by 4.) Since floating-point condition codes > can't store TImode, the backend should be ignoring them and > returning 2 instead. I'm testing a fix for that now. Here's what I applied after testing mips64-linux-gnu. As well as fixing the wrong value for valid combinations, it has the side-effect of returning an over-the-top value for more invalid combinations than before. That's semi- intentional though. I don't think this macro is required to detect invalid modes, or return a specific value for them. Richard gcc/ * config/mips/mips.c (mips_class_max_nregs): Check that the mode is OK for ST_REGS and FP_REGS before taking those classes into account. Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2011-08-20 19:44:44.000000000 +0100 +++ gcc/config/mips/mips.c 2011-08-20 19:49:06.000000000 +0100 @@ -10630,12 +10630,14 @@ mips_class_max_nregs (enum reg_class rcl COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) { - size = MIN (size, 4); + if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode)) + size = MIN (size, 4); AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); } if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) { - size = MIN (size, UNITS_PER_FPREG); + if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode)) + size = MIN (size, UNITS_PER_FPREG); AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); } if (!hard_reg_set_empty_p (left))