From patchwork Thu Nov 28 23:48:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1202306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-514806-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ytaNX3Rf"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47PDqh665rz9sPj for ; Fri, 29 Nov 2019 10:48:46 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=Cdh5eTR8kVGY JJQ9mnOU8raZ/jl992+KhzlYV2wI1A+wsi1r0bk5Y/ctnR+8VPGEhc+/AkNCyhY/ WmJshWcLRZ9fKRryrYThJdtHJymfcft1Yp/k+lHLBk6v+LNS10dC/5iy1Nv1rRLN ki5aerMH2gElTWn4Taagjjh+Wrw2ijQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=NH2cstXzOHOJJ+9kmq 5FqLu0LBE=; b=ytaNX3RfY7cBuXB7crH1sxn6gG2qzqTiEXtH4PICD9ZsctmhcJ K0ZGwRrzbI7PrQ5R1a6rCVDoqm/UXBlE9spt+KhQw+x6lJfc+rqXI8ISemkX675L i2kZxDQa5PIjfaWesweEJWvMH5CI9nlQKqjCpzExO/abirQsAeeadrbDo= Received: (qmail 20512 invoked by alias); 28 Nov 2019 23:48:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20499 invoked by uid 89); 28 Nov 2019 23:48:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 28 Nov 2019 23:48:37 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id D9EE8124073B; Thu, 28 Nov 2019 23:48:34 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool Subject: [PATCH] rs6000: Fix formatting of *mov{si,di}_internal.* Date: Thu, 28 Nov 2019 23:48:33 +0000 Message-Id: <81e949a5cd389ba55d5b32e229c28cea8e64aa95.1574984676.git.segher@kernel.crashing.org> X-IsSubscribed: yes This implements the improvements I asked for. Committing. Segher 2019-11-28 Segher Boessenkool * config/rs6000/rs6000.md (*movsi_internal1): Fix formatting. Improve formatting. (*movdi_internal64): Ditto. --- gcc/config/rs6000/rs6000.md | 192 ++++++++++++++++++++++---------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 876dfe3..e3e17ad 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6889,34 +6889,34 @@ (define_split UNSPEC_MOVSI_GOT))] "") -;; MR LA -;; LWZ LFIWZX LXSIWZX -;; STW STFIWX STXSIWX -;; LI LIS # -;; XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW -;; XXLXOR 0 XXLORC -1 P9 const -;; MTVSRWZ MFVSRWZ -;; MF%1 MT%0 NOP +;; MR LA +;; LWZ LFIWZX LXSIWZX +;; STW STFIWX STXSIWX +;; LI LIS # +;; XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW +;; XXLXOR 0 XXLORC -1 P9 const +;; MTVSRWZ MFVSRWZ +;; MF%1 MT%0 NOP (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "nonimmediate_operand" - "=r, r, - r, d, v, - m, Z, Z, - r, r, r, - wa, wa, wa, v, - wa, v, v, - wa, r, - r, *h, *h") + "=r, r, + r, d, v, + m, Z, Z, + r, r, r, + wa, wa, wa, v, + wa, v, v, + wa, r, + r, *h, *h") (match_operand:SI 1 "input_operand" - "r, U, - m, Z, Z, - r, d, v, - I, L, n, - wa, O, wM, wB, - O, wM, wS, - r, wa, - *h, r, 0"))] + "r, U, + m, Z, Z, + r, d, v, + I, L, n, + wa, O, wM, wB, + O, wM, wS, + r, wa, + *h, r, 0"))] "gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode)" "@ @@ -6944,32 +6944,32 @@ (define_insn "*movsi_internal1" mt%0 %1 nop" [(set_attr "type" - "*, *, - load, fpload, fpload, - store, fpstore, fpstore, - *, *, *, - veclogical, vecsimple, vecsimple, vecsimple, - veclogical, veclogical, vecsimple, - mffgpr, mftgpr, - *, *, *") + "*, *, + load, fpload, fpload, + store, fpstore, fpstore, + *, *, *, + veclogical, vecsimple, vecsimple, vecsimple, + veclogical, veclogical, vecsimple, + mffgpr, mftgpr, + *, *, *") (set_attr "length" - "*, *, - *, *, *, - *, *, *, - *, *, 8, - *, *, *, *, - *, *, 8, - *, *, - *, *, *") + "*, *, + *, *, *, + *, *, *, + *, *, 8, + *, *, *, *, + *, *, 8, + *, *, + *, *, *") (set_attr "isa" - "*, *, - *, p8v, p8v, - *, p8v, p8v, - *, *, *, - p8v, p9v, p9v, p8v, - p9v, p8v, p9v, - p8v, p8v, - *, *, *")]) + "*, *, + *, p8v, p8v, + *, p8v, p8v, + *, *, *, + p8v, p9v, p9v, p8v, + p9v, p8v, p9v, + p8v, p8v, + *, *, *")]) ;; Like movsi, but adjust a SF value to be used in a SI context, i.e. ;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0)) @@ -8827,33 +8827,33 @@ (define_split DONE; }) -;; GPR store GPR load GPR move -;; GPR li GPR lis GPR # -;; FPR store FPR load FPR move -;; AVX store AVX store AVX load AVX load VSX move -;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 -;; P9 const AVX const -;; From SPR To SPR SPR<->SPR -;; VSX->GPR GPR->VSX +;; GPR store GPR load GPR move +;; GPR li GPR lis GPR # +;; FPR store FPR load FPR move +;; AVX store AVX store AVX load AVX load VSX move +;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 +;; P9 const AVX const +;; From SPR To SPR SPR<->SPR +;; VSX->GPR GPR->VSX (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=YZ, r, r, - r, r, r, - m, ^d, ^d, - wY, Z, $v, $v, ^wa, - wa, wa, v, wa, wa, - v, v, - r, *h, *h, - ?r, ?wa") + "=YZ, r, r, + r, r, r, + m, ^d, ^d, + wY, Z, $v, $v, ^wa, + wa, wa, v, wa, wa, + v, v, + r, *h, *h, + ?r, ?wa") (match_operand:DI 1 "input_operand" - "r, YZ, r, - I, L, nF, - ^d, m, ^d, - ^v, $v, wY, Z, ^wa, - Oj, wM, OjwM, Oj, wM, - wS, wB, - *h, r, 0, - wa, r"))] + "r, YZ, r, + I, L, nF, + ^d, m, ^d, + ^v, $v, wY, Z, ^wa, + Oj, wM, OjwM, Oj, wM, + wS, wB, + *h, r, 0, + wa, r"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -8885,33 +8885,33 @@ (define_insn "*movdi_internal64" mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, - *, *, *, - fpstore, fpload, fpsimple, - fpstore, fpstore, fpload, fpload, veclogical, - vecsimple, vecsimple, vecsimple, veclogical, veclogical, - vecsimple, vecsimple, - mfjmpr, mtjmpr, *, - mftgpr, mffgpr") + "store, load, *, + *, *, *, + fpstore, fpload, fpsimple, + fpstore, fpstore, fpload, fpload, veclogical, + vecsimple, vecsimple, vecsimple, veclogical, veclogical, + vecsimple, vecsimple, + mfjmpr, mtjmpr, *, + mftgpr, mffgpr") (set_attr "size" "64") (set_attr "length" - "*, *, *, - *, *, 20, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - 8, *, - *, *, *, - *, *") + "*, *, *, + *, *, 20, + *, *, *, + *, *, *, *, *, + *, *, *, *, *, + 8, *, + *, *, *, + *, *") (set_attr "isa" - "*, *, *, - *, *, *, - *, *, *, - p9v, p7v, p9v, p7v, *, - p9v, p9v, p7v, *, *, - p7v, p7v, - *, *, *, - p8v, p8v")]) + "*, *, *, + *, *, *, + *, *, *, + p9v, p7v, p9v, p7v, *, + p9v, p9v, p7v, *, *, + p7v, p7v, + *, *, *, + p8v, p8v")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction.