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Rozycki" Mime-Version: 1.0 X-Lms-Return-Path: From: "Jie Mei" Subject: [PATCH v3 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions Message-Id: <7b8c006b3cd91120331c759b213bac49ad7a8286.1684918169.git.jie.mei@oss.cipunited.com> X-Mailer: git-send-email 2.40.1 To: Date: Wed, 24 May 2023 17:41:24 +0800 In-Reply-To: References: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, HTML_NONELEMENT_30_40, KAM_DMARC_STATUS, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and3_mips16): Generates ZEB/ZEH instructions. --- gcc/config/mips/mips.md | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7eb65891820..85ed1735d83 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3357,9 +3357,9 @@ (set_attr "mode" "")]) (define_insn "*and3_mips16" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0,d,0,0?") - (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d,d,d") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,W,W,W,d,0,d,0,0?") + (match_operand:GPR 2 "and_operand" "Yb,Yh,Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] "TARGET_MIPS16 && and_operands_ok (mode, operands[1], operands[2])" { int len; @@ -3368,38 +3368,42 @@ switch (which_alternative) { case 0: + return "zeb\t%0"; + case 1: + return "zeh\t%0"; + case 2: operands[1] = gen_lowpart (QImode, operands[1]); return "lbu\t%0,%1"; - case 1: + case 3: operands[1] = gen_lowpart (HImode, operands[1]); return "lhu\t%0,%1"; - case 2: + case 4: operands[1] = gen_lowpart (SImode, operands[1]); return "lwu\t%0,%1"; - case 3: + case 5: return "#"; - case 4: + case 6: return "and\t%0,%2"; - case 5: + case 7: len = low_bitmask_len (mode, INTVAL (operands[2])); operands[2] = GEN_INT (len); return "ext\t%0,%1,0,%2"; - case 6: + case 8: mips_bit_clear_info (mode, INTVAL (operands[2]), &pos, &len); operands[1] = GEN_INT (pos); operands[2] = GEN_INT (len); return "ins\t%0,$0,%1,%2"; - case 7: + case 9: return "andi\t%0,%x2"; default: gcc_unreachable (); } } - [(set_attr "move_type" "load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") + [(set_attr "move_type" "andi,andi,load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") (set_attr "mode" "") - (set_attr "extended_mips16" "no,no,no,no,no,yes,yes,yes") + (set_attr "extended_mips16" "no,no,no,no,no,no,no,yes,yes,yes") (set (attr "enabled") - (cond [(and (eq_attr "alternative" "7") + (cond [(and (eq_attr "alternative" "9") (not (match_test "ISA_HAS_MIPS16E2"))) (const_string "no") (and (eq_attr "alternative" "0,1")