From patchwork Tue Sep 16 00:58:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 389911 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0814614013A for ; Tue, 16 Sep 2014 10:58:43 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=t0EQYIgfgKm+ cYiramYeZD58aiFNXiZLrQKpzTTDpTB2z+EuKc3/pow9k8NnSkjlIqWWsbbrTRcP m6vxjvbY58I9GmwqWGN0cjkAkl0y0G2cL5X9xl+KMIIXzHyQpTdAVZDASiw8L9eo IT6rl9YLYtheaJ8mHvpw7LW0a6FupdU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=OXX0JVlabxpQgn0qDJ VpCJXpWyg=; b=VepRs7cy6mdkRqt47TG9HJQ4PoxCUOQssi4WagY2tYTTbybUAK CU3a8LsXvGyntUgqpBw4nOi02goycVv1n4DasJrUHkWHucvDhsECq+8iA4jwgWQ2 Y+2JAIEQoJyBc8ONgi1fMNrn6dQbhONaBE+jXmOLRxI4LMShIdiMIZe3k= Received: (qmail 22986 invoked by alias); 16 Sep 2014 00:58:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22971 invoked by uid 89); 16 Sep 2014 00:58:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 16 Sep 2014 00:58:32 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s8G0wUBF062334; Mon, 15 Sep 2014 17:58:30 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s8G0wPjI062296; Mon, 15 Sep 2014 17:58:25 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool Subject: [PATCH] Do not allow non-allocatable registers in scratch_operand Date: Mon, 15 Sep 2014 17:58:22 -0700 Message-Id: <74729933448c3ec81b326073757add5ddb1165a7.1410826448.git.segher@kernel.crashing.org> X-IsSubscribed: yes Currently, scratch_operand allows all hard registers, also those that cannot be allocated and are only generated explicitly by the backend. This causes problems. Consider the case where combine combines instructions A and B, where B clobbers such a non-allocatable hard reg X, into an instruction C that has a clobber of a match_scratch. Concretely for example: A is (set (reg:SI 98) (eq:SI ...)) B is (parallel [(set (reg:SI 99) (minus (const_int 1) (reg:SI 98))) (clobber (reg:SI CA_REGNO))]) so that combine tries an insn C (parallel [(set (reg:SI 99) (ne:SI ...)) (clobber (reg:SI CA_REGNO))]) which matches the pattern (parallel [(set (match_operand:SI 0 "..." "=r") (ne:SI ...)) (clobber (match_scratch:SI 3 "=r"))]) which is not going to work; it is not a valid insn. (In my testcase, reload eventually replaces CA_REGNO with a GPR that is not dead. Oops.) Combine shouldn't keep the original clobbers. But also, scratch_operand should not allow non-allocatable registers, since that can never work. This patch does the latter. Bootstrapped and regression checked on powerpc64-linux, with options -m32,-m32/-mpowerpc64,-m64,-m64/-mlra. No regressions, and testcase fixed (the testcase is forall_4.f90, it requires some backend patches to fail). Is this okay for mainline? Segher 2014-09-15 Segher Boessenkool * recog.c (scratch_operand): Do not simply allow all hard registers: only allow those that are allocatable. --- gcc/recog.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/recog.c b/gcc/recog.c index 2150b7a..6987afb 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -1143,7 +1143,9 @@ scratch_operand (rtx op, enum machine_mode mode) return (GET_CODE (op) == SCRATCH || (REG_P (op) - && (lra_in_progress || REGNO (op) < FIRST_PSEUDO_REGISTER))); + && (lra_in_progress + || (REGNO (op) < FIRST_PSEUDO_REGISTER + && REGNO_REG_CLASS (REGNO (op)) != NO_REGS)))); } /* Return 1 if OP is a valid immediate operand for mode MODE.