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Mon, 26 Apr 2021 16:36:01 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 13QGa0CY16908640 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 26 Apr 2021 16:36:00 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 38DF4C6055; Mon, 26 Apr 2021 16:36:00 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ACA4EC6057; Mon, 26 Apr 2021 16:35:59 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.163.16.179]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 26 Apr 2021 16:35:59 +0000 (GMT) Message-ID: <6eca12b01c738c688bf88194c5708af38324f7e9.camel@us.ibm.com> Subject: [PATCH 1/5 ver4] RS6000: Add 128-bit Integer Operations To: Segher Boessenkool , will schmidt , cel@us.ibm.com Date: Mon, 26 Apr 2021 09:35:58 -0700 In-Reply-To: References: X-Mailer: Evolution 3.28.5 (3.28.5-14.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: UOdrIG3ppQ3GTU6DbE3OrTRwVqpvyixP X-Proofpoint-ORIG-GUID: Jcpm4kLI7yyzBdMk6OL8ke3aCYyjHwk1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-26_09:2021-04-26, 2021-04-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 adultscore=0 suspectscore=0 clxscore=1015 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104260126 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Carl Love via Gcc-patches From: Carl Love Reply-To: Carl Love Cc: Peter Bergner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Will, Segher: This patch fixes the order of the argument in the vec_rlmi and vec_rlnm builtins. The patch also adds a new test cases to verify the fix. The patch has been tested on powerpc64-linux instead (Power 8 BE) powerpc64-linux instead (Power 9 LE) powerpc64-linux instead (Power 10 LE) Please let me know if the patch is acceptable for mainline. Carl Love ------------------------------------------------------------ 2021-04-26 Carl Love gcc/ * config/rs6000/altivec.md (altivec_vrlmi): Fix bug in argument generation. gcc/testsuite/ gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c: New runnable test case. gcc.target/powerpc/vec-rlmi-rlnm.c: Update scan assembler times for xxlor instruction. --- gcc/config/rs6000/altivec.md | 6 +- .../powerpc/check-builtin-vec_rlnm-runnable.c | 231 ++++++++++++++++++ .../gcc.target/powerpc/vec-rlmi-rlnm.c | 2 +- 3 files changed, 235 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 1351dafbc41..97dc9d2bda9 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1987,12 +1987,12 @@ (define_insn "altivec_vrlmi" [(set (match_operand:VIlong 0 "register_operand" "=v") - (unspec:VIlong [(match_operand:VIlong 1 "register_operand" "0") - (match_operand:VIlong 2 "register_operand" "v") + (unspec:VIlong [(match_operand:VIlong 1 "register_operand" "v") + (match_operand:VIlong 2 "register_operand" "0") (match_operand:VIlong 3 "register_operand" "v")] UNSPEC_VRLMI))] "TARGET_P9_VECTOR" - "vrlmi %0,%2,%3" + "vrlmi %0,%1,%3" [(set_attr "type" "veclogical")]) (define_insn "altivec_vrlnm" diff --git a/gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c b/gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c new file mode 100644 index 00000000000..be8f82d8a06 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c @@ -0,0 +1,231 @@ +/* { dg-do run } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -save-temps" } */ + +/* Verify the vec_rlm and vec_rlmi builtins works correctly. */ +/* { dg-final { scan-assembler-times {\mvrldmi\M} 1 } } */ + +#include + +#ifdef DEBUG +#include +#include +#endif + +void abort (void); + +int main () +{ + int i; + + vector unsigned int vec_arg1_int, vec_arg2_int, vec_arg3_int; + vector unsigned int vec_result_int, vec_expected_result_int; + + vector unsigned long long int vec_arg1_di, vec_arg2_di, vec_arg3_di; + vector unsigned long long int vec_result_di, vec_expected_result_di; + + unsigned int mask_begin, mask_end, shift; + unsigned long long int mask; + +/* Check vec int version of vec_rlmi builtin */ + mask = 0; + mask_begin = 0; + mask_end = 4; + shift = 16; + + for (i = 0; i < 31; i++) + if ((i >= mask_begin) && (i <= mask_end)) + mask |= 0x80000000ULL >> i; + + for (i = 0; i < 4; i++) { + vec_arg1_int[i] = 0x12345678 + i*0x11111111; + vec_arg2_int[i] = 0xA1B1CDEF; + vec_arg3_int[i] = mask_begin << 16 | mask_end << 8 | shift; + + /* do rotate */ + vec_expected_result_int[i] = ( vec_arg2_int[i] & ~mask) + | ((vec_arg1_int[i] << shift) | (vec_arg1_int[i] >> (32-shift))) & mask; + + } + + /* vec_rlmi(arg1, arg2, arg3) + result - rotate each element of arg2 left and inserting it into arg1 + element based on the mask specified in arg3. The shift, mask + start and end is specified in arg3. */ + vec_result_int = vec_rlmi (vec_arg1_int, vec_arg2_int, vec_arg3_int); + + for (i = 0; i < 4; i++) { + if (vec_result_int[i] != vec_expected_result_int[i]) +#ifdef DEBUG + printf("ERROR: i = %d, vec_rlmi int result 0x%x, does not match " + "expected result 0x%x\n", i, vec_result_int[i], + vec_expected_result_int[i]); +#else + abort(); +#endif + } + +/* Check vec long long int version of vec_rlmi builtin */ + mask = 0; + mask_begin = 0; + mask_end = 4; + shift = 16; + + for (i = 0; i < 31; i++) + if ((i >= mask_begin) && (i <= mask_end)) + mask |= 0x8000000000000000ULL >> i; + + for (i = 0; i < 2; i++) { + vec_arg1_di[i] = 0x1234567800000000 + i*0x11111111; + vec_arg2_di[i] = 0xA1B1C1D1E1F12345; + vec_arg3_di[i] = mask_begin << 16 | mask_end << 8 | shift; + + /* do rotate */ + vec_expected_result_di[i] = ( vec_arg2_di[i] & ~mask) + | ((vec_arg1_di[i] << shift) | (vec_arg1_di[i] >> (64-shift))) & mask; + } + + /* vec_rlmi(arg1, arg2, arg3) + result - rotate each element of arg1 left and inserting it into arg2 + element of arg2 based on the mask specified in arg3. The shift, mask + start and end is specified in arg3. */ + vec_result_di = vec_rlmi (vec_arg1_di, vec_arg2_di, vec_arg3_di); + + for (i = 0; i < 2; i++) { + if (vec_result_di[i] != vec_expected_result_di[i]) +#ifdef DEBUG + printf("ERROR: i = %d, vec_rlmi int long long result 0x%llx, does not match " + "expected result 0x%llx\n", i, vec_result_di[i], + vec_expected_result_di[i]); +#else + abort(); +#endif + } + + /* Check vec int version of vec_rlnm builtin */ + mask = 0; + mask_begin = 0; + mask_end = 4; + shift = 16; + + for (i = 0; i < 31; i++) + if ((i >= mask_begin) && (i <= mask_end)) + mask |= 0x80000000ULL >> i; + + for (i = 0; i < 4; i++) { + vec_arg1_int[i] = 0x12345678 + i*0x11111111; + vec_arg2_int[i] = shift; + vec_arg3_int[i] = mask_begin << 8 | mask_end; + vec_expected_result_int[i] = (vec_arg1_int[i] << shift) & mask; + } + + /* vec_rlnm(arg1, arg2, arg3) + result - rotate each element of arg1 left by shift in element of arg2. + Then AND with mask whose start/stop bits are specified in element of + arg3. */ + vec_result_int = vec_rlnm (vec_arg1_int, vec_arg2_int, vec_arg3_int); + for (i = 0; i < 4; i++) { + if (vec_result_int[i] != vec_expected_result_int[i]) +#ifdef DEBUG + printf("ERROR: vec_rlnm, i = %d, int result 0x%x does not match " + "expected result 0x%x\n", i, vec_result_int[i], + vec_expected_result_int[i]); +#else + abort(); +#endif + } + +/* Check vec long int version of builtin */ + mask = 0; + mask_begin = 0; + mask_end = 4; + shift = 20; + + for (i = 0; i < 63; i++) + if ((i >= mask_begin) && (i <= mask_end)) + mask |= 0x8000000000000000ULL >> i; + + for (i = 0; i < 2; i++) { + vec_arg1_di[i] = 0x123456789ABCDE00ULL + i*0x1111111111111111ULL; + vec_arg2_di[i] = shift; + vec_arg3_di[i] = mask_begin << 8 | mask_end; + vec_expected_result_di[i] = (vec_arg1_di[i] << shift) & mask; + } + + vec_result_di = vec_rlnm (vec_arg1_di, vec_arg2_di, vec_arg3_di); + + for (i = 0; i < 2; i++) { + if (vec_result_di[i] != vec_expected_result_di[i]) +#ifdef DEBUG + printf("ERROR: vec_rlnm, i = %d, long long int result 0x%llx does not " + "match expected result 0x%llx\n", i, vec_result_di[i], + vec_expected_result_di[i]); +#else + abort(); +#endif + } + + /* Check vec int version of vec_vrlnm builtin */ + mask = 0; + mask_begin = 0; + mask_end = 4; + shift = 16; + + for (i = 0; i < 31; i++) + if ((i >= mask_begin) && (i <= mask_end)) + mask |= 0x80000000ULL >> i; + + for (i = 0; i < 4; i++) { + vec_arg1_int[i] = 0x12345678 + i*0x11111111; + vec_arg2_int[i] = mask_begin << 16 | mask_end << 8 | shift; + vec_expected_result_int[i] = (vec_arg1_int[i] << shift) & mask; + } + + /* vec_vrlnm(arg1, arg2, arg3) + result - rotate each element of arg1 left then AND with mask. The mask + start, stop bits is specified in the second argument. The shift amount + is also specified in the second argument. */ + vec_result_int = vec_vrlnm (vec_arg1_int, vec_arg2_int); + + for (i = 0; i < 4; i++) { + if (vec_result_int[i] != vec_expected_result_int[i]) +#ifdef DEBUG + printf("ERROR: vec_vrlnm, i = %d, int result 0x%x does not match " + "expected result 0x%x\n", i, vec_result_int[i], + vec_expected_result_int[i]); +#else + abort(); +#endif + } + +/* Check vec long int version of vec_vrlnm builtin */ + mask = 0; + mask_begin = 0; + mask_end = 4; + shift = 20; + + for (i = 0; i < 63; i++) + if ((i >= mask_begin) && (i <= mask_end)) + mask |= 0x8000000000000000ULL >> i; + + for (i = 0; i < 2; i++) { + vec_arg1_di[i] = 0x123456789ABCDE00ULL + i*0x1111111111111111ULL; + vec_arg2_di[i] = mask_begin << 16 | mask_end << 8 | shift; + vec_expected_result_di[i] = (vec_arg1_di[i] << shift) & mask; + } + + vec_result_di = vec_vrlnm (vec_arg1_di, vec_arg2_di); + + for (i = 0; i < 2; i++) { + if (vec_result_di[i] != vec_expected_result_di[i]) +#ifdef DEBUG + printf("ERROR: vec_vrlnm, i = %d, long long int result 0x%llx does not " + "match expected result 0x%llx\n", i, vec_result_di[i], + vec_expected_result_di[i]); +#else + abort(); +#endif + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c index 1e7d7390c5b..b0f26c8f4cb 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c @@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned long long y, /* { dg-final { scan-assembler-times "vextsb2d" 1 } } */ /* { dg-final { scan-assembler-times "vslw" 1 } } */ /* { dg-final { scan-assembler-times "vsld" 1 } } */ -/* { dg-final { scan-assembler-times "xxlor" 3 } } */ +/* { dg-final { scan-assembler-times "xxlor" 5 } } */ /* { dg-final { scan-assembler-times "vrlwnm" 2 } } */ /* { dg-final { scan-assembler-times "vrldnm" 2 } } */