diff mbox series

[1/4] aarch64: encourage use of GPR input for SIMD inserts

Message ID 6bdb70e9-8c02-2c91-9ec3-33004a67c3ed@arm.com
State New
Headers show
Series aarch64: Improve codegen for dups and constructors | expand

Commit Message

Andre Vieira (lists) Aug. 5, 2022, 12:53 p.m. UTC 
Hi,

This enables and makes it more likely the compiler is able to use GPR 
input for SIMD inserts. I believe this is some outdated hack we used to 
prevent costly GPR<->SIMD register file swaps. This patch is required 
for better codegen in situations like the test case 'int8_3' in the next 
patch in this series.

Bootstrapped and regression tested together with the next patch on 
aarch64-none-linux-gnu.

gcc/ChangeLog:

2022-08-05  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): 
Remove '?' modifier.
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 587a45d77721e1b39accbad7dbeca4d741eccb10..51eab5a872ade7b70268676346e8be7c9c6c8e3a 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1038,7 +1038,7 @@ 
   [(set (match_operand:VALL_F16 0 "register_operand" "=w,w,w")
 	(vec_merge:VALL_F16
 	    (vec_duplicate:VALL_F16
-		(match_operand:<VEL> 1 "aarch64_simd_nonimmediate_operand" "w,?r,Utv"))
+		(match_operand:<VEL> 1 "aarch64_simd_nonimmediate_operand" "w,r,Utv"))
 	    (match_operand:VALL_F16 3 "register_operand" "0,0,0")
 	    (match_operand:SI 2 "immediate_operand" "i,i,i")))]
   "TARGET_SIMD"