From patchwork Tue Jun 6 10:56:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Renlin Li X-Patchwork-Id: 771771 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3whpY20wyrz9s7h for ; Tue, 6 Jun 2017 20:57:08 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="tHKaJ1FT"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=BwcpXvVpkoCNeugNtTd/Pc5IRoI4Mi4DqtPnOLo3NExjRRBUYv Ayf+ufM1026iRij7sNVT4rJ73j6NY6flNWI6/BUHLSoIisVoMhSYzcqd0L1ObCIu b3ZD7a9LdNH08yDuuAKDLwYQGuKVBOopE2jBGAUczBRWzsSr+XHuXft9o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; s= default; bh=MK9Arw6MOel7XNx+Vcvy4wVrGVM=; b=tHKaJ1FTkFYKhbsPdoGP HwM7KVqFefZeEAhB1bxaiTYOk8l1jOR7/8YfcpZsdK0NSyOqvLr9yiHgko6udY0o 2PWaLgj/uqtvQwWOXI9GEmxbmgIBkeqk57qhqxreum+mj/RfNk/6F9X8YszBOVUM LxLOkbE91aEBQDX89K1xFM0= Received: (qmail 33714 invoked by alias); 6 Jun 2017 10:56:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 33299 invoked by uid 89); 6 Jun 2017 10:56:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=UINTVAL, uintval, 84939 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Jun 2017 10:56:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 793DD1596; Tue, 6 Jun 2017 03:56:54 -0700 (PDT) Received: from [10.2.207.43] (e104453-lin.cambridge.arm.com [10.2.207.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87D033F587; Tue, 6 Jun 2017 03:56:53 -0700 (PDT) To: "gcc-patches@gcc.gnu.org" Cc: James Greenhalgh , Ramana Radhakrishnan , Andrew Pinski , Richard Earnshaw From: Renlin Li Subject: [RFC][AARCH64]Add 'r' integer register operand modifier. Document the common asm modifier for aarch64 target. Message-ID: <59368A74.2060908@foss.arm.com> Date: Tue, 6 Jun 2017 11:56:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi all, In this patch, a new integer register operand modifier 'r' is added. This will use the proper register name according to the mode of corresponding operand. 'w' register for scalar integer mode smaller than DImode 'x' register for DImode This allows more flexibility and would meet people's expectations. It will help for ILP32 and LP64, and big-endian case. A new section is added to document the AArch64 operand modifiers which might be used in inline assembly. It's not an exhaustive list covers every modifier. Only the most common and useful ones are documented. The default behavior of integer operand without modifier is clearly documented as well. It's not changed so that the patch shouldn't break anything. So with this patch, it should resolve the issues in PR63359. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 aarch64-none-elf regression test Okay. Okay to check in? gcc/ChangeLog: 2017-06-06 Renlin Li PR target/63359 * config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' modifier. * doc/extend.texi (AArch64Operandmodifiers): New section. commit f8725ffd1375a8347cc8f4f183262c08ce2f73c6 Author: Renlin Li Date: Tue May 23 16:46:31 2017 +0100 [AARCH64]Add 'r' integer operand modifier. Document the be extend asm modifier for aarch64 target. gcc/ChangeLog: PR target/63359 * config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' modifier. * doc/extend.texi (AArch64Operandmodifiers): New section. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5707e53..d1c400f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5132,6 +5132,26 @@ aarch64_print_operand (FILE *f, rtx x, int code) asm_fprintf (f, "0x%wx", UINTVAL (x) & 0xffff); break; + case 'r': + { + machine_mode mode = GET_MODE (x); + switch (mode) + { + case QImode: + case HImode: + case SImode: + code = 'w'; + break; + case DImode: + code = 'x'; + break; + default: + output_operand_lossage + ("invalid operand mode for register modifier 'r'"); + } + } + /* Fall through. */ + case 'w': case 'x': /* Print a general register name or the zero register (32-bit or diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 60a1a3f..d1c830d 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -8264,7 +8264,9 @@ is undefined if @var{a} is modified before using @var{b}. @code{asm} supports operand modifiers on operands (for example @samp{%k2} instead of simply @samp{%2}). Typically these qualifiers are hardware dependent. The list of supported modifiers for x86 is found at -@ref{x86Operandmodifiers,x86 Operand modifiers}. +@ref{x86Operandmodifiers,x86 Operand modifiers}. The list of supported +modifiers for AArch64 is found at +@ref{AArch64Operandmodifiers,AArch64 Operand modifiers}. If the C code that follows the @code{asm} makes no use of any of the output operands, use @code{volatile} for the @code{asm} statement to prevent the @@ -8491,7 +8493,9 @@ optimizers may discard the @code{asm} statement as unneeded @code{asm} supports operand modifiers on operands (for example @samp{%k2} instead of simply @samp{%2}). Typically these qualifiers are hardware dependent. The list of supported modifiers for x86 is found at -@ref{x86Operandmodifiers,x86 Operand modifiers}. +@ref{x86Operandmodifiers,x86 Operand modifiers}. The list of supported +modifiers for AArch64 is found at +@ref{AArch64Operandmodifiers,AArch64 Operand modifiers}. In this example using the fictitious @code{combine} instruction, the constraint @code{"0"} for input operand 1 says that it must occupy the same @@ -8659,6 +8663,70 @@ error: @} @end example +@anchor{AArch64Operandmodifiers} +@subsubsection AArch64 Operand Modifiers +References to input, output, and goto operands in the assembler template +of extended @code{asm} statements can use +modifiers to affect the way the operands are formatted in +the code output to the assembler. + +The table blow descirbes the list of useful register operand modifiers which +might be used in extended @code{asm}. It is not necessary a complete list +of modifiers supported by the AArch64 backend. + +@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand} +@headitem Modifier @tab Description @tab Operand +@item @code{r} +@tab Print the opcode suffix for the size of the current integer operand (one of @code{w}/@code{x}). +@tab @code{%r0} +@item @code{w} +@tab Print the SImode name of the register. +@tab @code{%w0} +@item @code{x} +@tab Print the DImode name of the register. +@tab @code{%x0} +@item @code{h} +@tab Print the HFmode name of the register. +@tab @code{%h0} +@item @code{s} +@tab Print the SFmode name of the register. +@tab @code{%s0} +@item @code{d} +@tab Print the DFmode name of the register. +@tab @code{%d0} +@item @code{q} +@tab Print the TFmode name of the register. +@tab @code{%q0} +@end multitable + +Without specifying any modifiers to a register operand, the default @code{x} +register name is used for integer operand, @code{v} register name is used for +floating pointer operand. For example: + +@example +int load_int (int *ptr, int offset) +@{ + int result; + asm ("ldr %0, [%1, %2]\n\t" + : "=r" (result) + : "r" (ptr), "r"(offset)); + return result; +@} +@end example + +The following code will be generated: + +@smallexample +ldr x0, [x0, x1] +@end smallexample + +If proper modifier is used for the first operand @code{result}, say @code{w} or +@code{r}, it will generate the following code as one would expected: + +@smallexample +ldr w0, [x0, x1] +@end smallexample + @anchor{x86Operandmodifiers} @subsubsection x86 Operand Modifiers