From patchwork Mon Feb 29 23:11:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evandro Menezes X-Patchwork-Id: 590218 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 25B2B140783 for ; Tue, 1 Mar 2016 10:11:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=vaaXSQEa; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=PrWTT94R8wTqXgxmm IClcEOvH4GFH6yDQxlfK9Wxr3rimAmasSew8L65shu51BNfTsBwSSEeDhn4cIAFS H0lMqn83PEC+LKXMhBW3/x7vk9tgLxS9vboIuIb1UlOW8NHCgFkPRNOCHHVmKIw6 5A/KLp80mBD6OIA1FyL4Lhi1A0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=VL86fNaYU4wiWf9DJtoEhGw Lglw=; b=vaaXSQEa7EecwmHf2fHInVKXe1yyGAgoHRgbBrIuJS64ITj2El2Sja0 fMv1x/yHT4i49VTN6JcuSdTCgJIprj70qzglqqNzE2YgkyHam85IvVdT5dzrx7ke VZ6BHlmbqhS4VE+BM4KzGDHFlC72o2aMLv+q9FXsXv5dHGXvHcoE= Received: (qmail 106760 invoked by alias); 29 Feb 2016 23:11:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 106735 invoked by uid 89); 29 Feb 2016 23:11:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.6 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=HContent-type:mixed, sk:nonimme, general_operand, rww X-HELO: usmailout3.samsung.com Received: from mailout3.w2.samsung.com (HELO usmailout3.samsung.com) (211.189.100.13) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 29 Feb 2016 23:11:45 +0000 Received: from uscpsbgm2.samsung.com (u115.gpu85.samsung.co.kr [203.254.195.115]) by usmailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O3C00KK30FISY20@usmailout3.samsung.com> for gcc-patches@gcc.gnu.org; Mon, 29 Feb 2016 18:11:42 -0500 (EST) Received: from ussync1.samsung.com ( [203.254.195.81]) by uscpsbgm2.samsung.com (USCPMTA) with SMTP id 4B.76.07641.E20D4D65; Mon, 29 Feb 2016 18:11:42 -0500 (EST) Received: from [172.31.207.192] ([105.140.31.209]) by ussync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O3C00DIA0FH0F50@ussync1.samsung.com>; Mon, 29 Feb 2016 18:11:42 -0500 (EST) Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register To: Wilco Dijkstra References: <56A94F35.8000000@samsung.com> <56D0D50E.8030802@samsung.com> Cc: "gcc-patches@gcc.gnu.org" , nd , Marcus Shawcroft , Kyrylo Tkachov , James Greenhalgh From: Evandro Menezes Message-id: <56D4D02C.6030309@samsung.com> Date: Mon, 29 Feb 2016 17:11:40 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-version: 1.0 In-reply-to: Content-type: multipart/mixed; boundary=------------070705000808030006050800 X-IsSubscribed: yes On 02/29/16 12:07, Wilco Dijkstra wrote: > Evandro Menezes wrote: >> Please, verify the new "simd" and "fp" attributes for SF and DF. > Both movsf and movdf should be: > > (set_attr "simd" "*,yes,*,*,*,*,*,*,*,*") > (set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*") > > Did you check that with -mcpu=generic+nosimd you get fmov s0, wzr? > In my version I kept the Y on the fmov and placed the neon_mov first. The meaning of these attributes are not clear to me. Is there a reference somewhere about which insns are FP or SIMD or neither? Indeed, I had to add the Y for the f_mcr insn to match it with nosimd. However, I didn't feel that it should be moved to the right, since it's already disparaged. Am I missing something detail? Thank you for the review, From 952c0f74da98efd7fcb37b2cfe3c17518a619088 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 19 Oct 2015 18:31:48 -0500 Subject: [PATCH] Replace insn to zero up SIMD registers gcc/ * config/aarch64/aarch64.md (*movhf_aarch64): Add "movi %0, #0" to zero up register. (*movsf_aarch64): Likewise and add "simd" and "fp" attributes. (*movdf_aarch64): Likewise. --- gcc/config/aarch64/aarch64.md | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 68676c9..416e065 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1163,12 +1163,13 @@ ) (define_insn "*movhf_aarch64" - [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r") - (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] + [(set (match_operand:HF 0 "nonimmediate_operand" "=w, w,?r,w,w,m,r,m ,r") + (match_operand:HF 1 "general_operand" "?rY,Y, w,w,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ mov\\t%0.h[0], %w1 + movi\\t%0.4h, #0 umov\\t%w0, %1.h[0] mov\\t%0.h[0], %1.h[0] ldr\\t%h0, %1 @@ -1176,19 +1177,20 @@ ldrh\\t%w0, %1 strh\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\ + [(set_attr "type" "neon_from_gp,neon_move,neon_to_gp,neon_move,\ f_loads,f_stores,load1,store1,mov_reg") - (set_attr "simd" "yes,yes,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,yes,yes,*,*,*")] + (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*") + (set_attr "fp" "*,*,*,*,yes,yes,*,*,*")] ) (define_insn "*movsf_aarch64" - [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=w, w,?r,w,w ,w,m,r,m ,r") + (match_operand:SF 1 "general_operand" "?rY,Y, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ fmov\\t%s0, %w1 + movi\\t%0.2s, #0 fmov\\t%w0, %s1 fmov\\t%s0, %s1 fmov\\t%s0, %1 @@ -1197,17 +1199,20 @@ ldr\\t%w0, %1 str\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,load1,store1,mov_reg")] + [(set_attr "type" "f_mcr,neon_move,f_mrc,fmov,fconsts,\ + f_loads,f_stores,load1,store1,mov_reg") + (set_attr "simd" "*,yes,*,*,*,*,*,*,*,*") + (set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*")] ) (define_insn "*movdf_aarch64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=w, w,?r,w,w ,w,m,r,m ,r") + (match_operand:DF 1 "general_operand" "?rY,Y, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ fmov\\t%d0, %x1 + movi\\t%d0, #0 fmov\\t%x0, %d1 fmov\\t%d0, %d1 fmov\\t%d0, %1 @@ -1216,8 +1221,10 @@ ldr\\t%x0, %1 str\\t%x1, %0 mov\\t%x0, %x1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,load1,store1,mov_reg")] + [(set_attr "type" "f_mcr,neon_move,f_mrc,fmov,fconstd,\ + f_loadd,f_stored,load1,store1,mov_reg") + (set_attr "simd" "*,yes,*,*,*,*,*,*,*,*") + (set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*")] ) (define_insn "*movtf_aarch64" -- 2.6.3