From patchwork Thu Jun 4 13:36:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Renlin Li X-Patchwork-Id: 480739 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BBD9F140271 for ; Thu, 4 Jun 2015 23:36:24 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Lqlq7EKD; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=ZQ/6mcj98HXmnqjS/ dadoaclcivoiXHGfIR6m7HskVtUflCYtZk6Caluiu+dm0+dqG4LQDH9iMWd6XK2D lbIqEYowtKO17wHQYR1Qdrkoir1NjfZWRdpmlWcoQefFRYPp5jP6KIaYe6PfbfUy w2PLGhkhFOAl3JQdFW0t3dWYjA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=jhoztNR4Je4PAjOIUA0XiDv vqus=; b=Lqlq7EKDzuW/oJlU3Stdv7NQdaZwbT1ltcqg+0Hbd1gmH4U0yNf4T6l tHir0eS9yXAh+eP8MaU+X6bnqBIKyk18UiJKU9hqKcn4tJFnJ3BqPPeD6EsexMce qjJuWNxXsM3qj78Gjvl2iJHhTJoc7t9/fsp8zfmsiBSrmyazPfuc= Received: (qmail 50238 invoked by alias); 4 Jun 2015 13:36:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 50228 invoked by uid 89); 4 Jun 2015 13:36:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 04 Jun 2015 13:36:15 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-34.uk.mimecast.lan; Thu, 04 Jun 2015 14:36:12 +0100 Received: from [10.2.207.43] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Jun 2015 14:36:11 +0100 Message-ID: <5570544B.8000508@arm.com> Date: Thu, 04 Jun 2015 14:36:11 +0100 From: Renlin Li User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Marcus Shawcroft CC: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Ramana Radhakrishnan , Andrew Pinski Subject: Re: Re: [PATCH][AARCH64]Add ACLE 2.0 predefined macros: __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR References: In-Reply-To: X-MC-Unique: xc2DGjSiTPWrYDY6qgz8tw-1 X-IsSubscribed: yes On 29/04/15 11:58, Marcus Shawcroft wrote: > On 29 April 2015 at 01:24, Andrew Pinski wrote: >> On Tue, Dec 16, 2014 at 2:19 AM, Renlin Li wrote: >>> Hi all, >>> >>> This is a simple patch to add another two ACLE 2.0 predefined macros into >>> aarch64 backend. >>> They are __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR. Currently, those >>> two values are hard-wired to 16. >>> >>> The following clauses from ACLE 2.0 documentation indicate the meaning of >>> those two macros: >>> >>> The macro __ARM_ALIGN_MAX_STACK_PWR indicates (as the exponent of a power of >>> 2) the maximum available stack alignment. >>> The macro __ARM_ALIGN_MAX_PWR indicates (as the exponent of a power of 2) >>> the maximum available alignment of static data. >>> >>> aarch64-none-elf target is tested on on the model. No new regression. >>> >>> Is it Okay for trunk? >> Have you tested these alignments? That is have we tested 65536 >> alignment for both stack and static data? >> I suspect the stack alignment that is support is not 64k but much >> smaller. And the supported static data alignment is much larger, >> maybe 20 or more. > Looks to me __ARM_ALIGN_MAX_STACK_PWR can be lifted to 2^16 without > issue. GCC won't gripe about the static data alignment until 2^29. > Aside from the latter being rather conservative I think we should add > a test case to the testsuite for each. RenLin can you prep a testcase? > > /Marcus Hi Marcus, Sorry for the delay. I have come up with an updated patch. Two test cases are added to check against the limit. __ARM_ALIGN_MAX_STACK_PWR is hard coded into 16. __ARM_ALIGN_MAX_PWR is hard coded into 28 which is the maximum allowable alignment user can define for aarch64 backend. Okay to commit on trunk, and backport to 5.0? Regards, Renlin Li gcc/ChangeLog: 2015-06-04 Renlin Li * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Add __ARM_ALIGN_MAX_PWR, __ARM_ALIGN_MAX_STACK_PWR. gcc/testsuite/ChangeLog: 2015-06-04 Renlin Li * gcc.target/aarch64/arm_align_max_pwr.c: New. * gcc.target/aarch64/arm_align_max_stack_pwr.c: New. diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 25b9927..085148d 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -29,6 +29,10 @@ builtin_define ("__aarch64__"); \ builtin_define ("__ARM_64BIT_STATE"); \ builtin_define_with_int_value \ + ("__ARM_ALIGN_MAX_PWR", 28); \ + builtin_define_with_int_value \ + ("__ARM_ALIGN_MAX_STACK_PWR", 16); \ + builtin_define_with_int_value \ ("__ARM_ARCH", aarch64_architecture_version); \ cpp_define_formatted \ (parse_in, "__ARM_ARCH_%dA", aarch64_architecture_version); \ diff --git a/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c b/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c new file mode 100644 index 0000000..d8471f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ + +#include +#include + +#define align (1ul << __ARM_ALIGN_MAX_PWR) +static int x __attribute__ ((aligned (align))); + +int +main () +{ + assert ((((unsigned long)&x) & (align - 1)) == 0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c b/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c new file mode 100644 index 0000000..e2e7900 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ + +#include +#include + +#define align (1ul << __ARM_ALIGN_MAX_STACK_PWR) + +int +main () +{ + int x __attribute__ ((aligned (align))); + + assert ((((unsigned long)&x) & (align - 1)) == 0); + return 0; +}