From patchwork Wed Dec 18 15:28:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 302917 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3A27A2C009A for ; Thu, 19 Dec 2013 02:29:37 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=MqsF9i2QIXWPYoFU9 uDP4H6rcg0nL8FnoKx7T/Lpcje7sbDWMO9V7HLyTcdvZihbd1etZez7ZbXsQn/BP jGZ9BzPJIoM2mf/LfZaUiTJOgX7I6Kf/QUCGy1gilrNvjJyhOtbpDqYLmikcmUun e1ccyHVeMmOWvuArzLRIdarR+c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=pjg+ccANswsCm9uTSfupDnh OfFQ=; b=BSZJOGk20IQGSm7ULUmqHz+y6M9hjrgjunZj/aM1Zcf8LqAVm1Dj62E 7hIZX6LYQUL6b55bvl/Iw9W25Lh5r9OhwrjR8utWTo+Bel9LnRayyNUlfFbF9uT6 qhpstUhl8uiLbMLaV0Dk5+9T5J9U729y6+IX2TQ/Xjm43O3Y4nYA= Received: (qmail 7496 invoked by alias); 18 Dec 2013 15:28:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 7446 invoked by uid 89); 18 Dec 2013 15:28:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 18 Dec 2013 15:28:52 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 18 Dec 2013 15:28:50 +0000 Received: from [10.1.203.80] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 18 Dec 2013 15:28:49 +0000 Message-ID: <52B1BF30.4040706@arm.com> Date: Wed, 18 Dec 2013 15:28:48 +0000 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: Marcus Shawcroft CC: "gcc-patches@gcc.gnu.org" Subject: Re: [Patch, AArch64] [5/6] Implement support for Crypto -- SHA256. References: <52A20B17.1070202@arm.com> In-Reply-To: X-MC-Unique: 113121815285003801 X-IsSubscribed: yes Marcus Shawcroft wrote: > On 6 December 2013 17:36, Tejas Belagod wrote: >> Hi, >> >> The attached patch implements support for crypto sha256. > > Same comments as previous crypto patch. Thanks for the review. Here is an improved patch. Tested on aarch64-none-elf. OK for trunk? Thanks Tejas. 2013-12-18 Tejas Belagod gcc/ * config/aarch64/aarch64-simd-builtins.def: Update builtins table. * config/aarch64/aarch64-simd.md (aarch64_crypto_sha256hv4si, aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New. * config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32, vsha256su0q_u32, vsha256su1q_u32): New. * config/aarch64/iterators.md (UNSPEC_SHA256H<2>, UNSPEC_SHA256SU<01>): New. (CRYPTO_SHA256): New int iterator. (sha256_op): New int attribute. testsuite/ * gcc.target/aarch64/sha256_1.c: New. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 2d3ccb0..adda948 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -380,3 +380,9 @@ VAR1 (TERNOPU, crypto_sha1m, 0, v4si) VAR1 (TERNOPU, crypto_sha1p, 0, v4si) VAR1 (TERNOPU, crypto_sha1su0, 0, v4si) + + /* Implemented by aarch64_crypto_sha256. */ + VAR1 (TERNOPU, crypto_sha256h, 0, v4si) + VAR1 (TERNOPU, crypto_sha256h2, 0, v4si) + VAR1 (BINOPU, crypto_sha256su0, 0, v4si) + VAR1 (TERNOPU, crypto_sha256su1, 0, v4si) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5b454ca..874d532 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4139,3 +4139,37 @@ "sha1su0\\t%0.4s, %2.4s, %3.4s" [(set_attr "type" "crypto_sha1_xor")] ) + +;; sha256 + +(define_insn "aarch64_crypto_sha256hv4si" + [(set (match_operand:V4SI 0 "register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "w") + (match_operand:V4SI 3 "register_operand" "w")] + CRYPTO_SHA256))] + "TARGET_SIMD && TARGET_CRYPTO" + "sha256h\\t%q0, %q2, %3.4s" + [(set_attr "type" "crypto_sha256_slow")] +) + +(define_insn "aarch64_crypto_sha256su0v4si" + [(set (match_operand:V4SI 0 "register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "w")] + UNSPEC_SHA256SU0))] + "TARGET_SIMD &&TARGET_CRYPTO" + "sha256su0\\t%0.4s, %2.4s" + [(set_attr "type" "crypto_sha256_fast")] +) + +(define_insn "aarch64_crypto_sha256su1v4si" + [(set (match_operand:V4SI 0 "register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "w") + (match_operand:V4SI 3 "register_operand" "w")] + UNSPEC_SHA256SU1))] + "TARGET_SIMD &&TARGET_CRYPTO" + "sha256su1\\t%0.4s, %2.4s, %3.4s" + [(set_attr "type" "crypto_sha256_slow")] +) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 5a5691d..709c6a1 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -22990,6 +22990,30 @@ vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15) return __builtin_aarch64_crypto_sha1su1v4si_uuu (tw0_3, w12_15); } +static __inline uint32x4_t +vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) +{ + return __builtin_aarch64_crypto_sha256hv4si_uuuu (hash_abcd, hash_efgh, wk); +} + +static __inline uint32x4_t +vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) +{ + return __builtin_aarch64_crypto_sha256h2v4si_uuuu (hash_efgh, hash_abcd, wk); +} + +static __inline uint32x4_t +vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7) +{ + return __builtin_aarch64_crypto_sha256su0v4si_uuu (w0_3, w4_7); +} + +static __inline uint32x4_t +vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15) +{ + return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15); +} + #endif /* vshl */ diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 12de4ac..88edddd 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -277,6 +277,10 @@ UNSPEC_SHA1H ; Used in aarch64-simd.md. UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. + UNSPEC_SHA256H ; Used in aarch64-simd.md. + UNSPEC_SHA256H2 ; Used in aarch64-simd.md. + UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. + UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------- @@ -863,6 +867,8 @@ (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) +(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) + ;; ------------------------------------------------------------------- ;; Int Iterators Attributes. ;; ------------------------------------------------------------------- @@ -985,3 +991,5 @@ (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") (UNSPEC_SHA1M "m")]) + +(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) diff --git a/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc/testsuite/gcc.target/aarch64/sha256_1.c new file mode 100644 index 0000000..569817e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sha256_1.c @@ -0,0 +1,40 @@ + +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+crypto" } */ + +#include "arm_neon.h" + +uint32x4_t +test_vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) +{ + return vsha256hq_u32 (hash_abcd, hash_efgh, wk); +} + +/* { dg-final { scan-assembler-times "sha256h\\tq" 1 } } */ + +uint32x4_t +test_vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) +{ + return vsha256h2q_u32 (hash_efgh, hash_abcd, wk); +} + +/* { dg-final { scan-assembler-times "sha256h2\\tq" 1 } } */ + +uint32x4_t +test_vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7) +{ + return vsha256su0q_u32 (w0_3, w4_7); +} + +/* { dg-final { scan-assembler-times "sha256su0\\tv" 1 } } */ + +uint32x4_t +test_vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15) +{ + return vsha256su1q_u32 (tw0_3, w8_11, w12_15); +} + +/* { dg-final { scan-assembler-times "sha256su1\\tv" 1 } } */ + + +/* { dg-final { cleanup-saved-temps } } */