From patchwork Wed Dec 18 15:28:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 302915 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D8D972C007B for ; Thu, 19 Dec 2013 02:29:05 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=qjLiWm5w0ouHgrFAS M6qE6ceWlnSakGb2FhL1TEyHG757ZDGHqxLFGkybQwecbKHHr6HqtJtq8OOp4QQL M7As2Ct3qjw/egIp7jmOr0kL8XByiD7I+svtBvehWeo1EaoY5ojy5/FoZS0yC30G zdSqPmzFg0ObaOircLEGcyWS/Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=AnvlSxxGWG9plqsHFU4Qxgl 1iP4=; b=IlAIg/xuqaDEKCe/6RoSTBMryljjBamgdTRXk3qR0ZfVlx4XKAo7FFU ugIS/xsmQRz3rreesX3Hgef5am6BQNoEdNl3AxNhHK56OTevbtwvSpTW2vPiKYyu O35QBdl9zgVZrDSK7FLwAbk41Q4qG+t0KMOG3dbUNdez38DLwWmA= Received: (qmail 5847 invoked by alias); 18 Dec 2013 15:28:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5757 invoked by uid 89); 18 Dec 2013 15:28:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 18 Dec 2013 15:28:27 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 18 Dec 2013 15:28:23 +0000 Received: from [10.1.203.80] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 18 Dec 2013 15:28:23 +0000 Message-ID: <52B1BF16.6030302@arm.com> Date: Wed, 18 Dec 2013 15:28:22 +0000 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: Marcus Shawcroft CC: "gcc-patches@gcc.gnu.org" Subject: Re: [Patch, AArch64] [3/6] Implement support for Crypto -- AES. References: <52A20B03.8050407@arm.com> In-Reply-To: X-MC-Unique: 113121815282301201 X-IsSubscribed: yes Marcus Shawcroft wrote: > On 6 December 2013 17:36, Tejas Belagod wrote: > >> * gcc.target/aarch64/aes.c: New. > > Add _1 on the test case file name (see http://gcc.gnu.org/wiki/TestCaseWriting) > > >> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h >> index dc56170..9f35e09 100644 >> --- a/gcc/config/aarch64/arm_neon.h >> +++ b/gcc/config/aarch64/arm_neon.h >> @@ -15793,6 +15793,42 @@ vaddvq_f64 (float64x2_t __a) >> return vgetq_lane_f64 (__t, __LANE0 (2)); >> } >> >> +#ifdef __ARM_FEATURE_CRYPTO >> + >> +/* vaes */ >> + >> +static __inline uint8x16_t >> +vaeseq_u8 (uint8x16_t data, uint8x16_t key) >> +{ >> + return >> + (uint8x16_t) __builtin_aarch64_crypto_aesev16qi ((int8x16_t) data, >> + (int8x16_t) key); > > James G fixed the infrastructure to allow properly typed builtins, see: > > http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02005.html > and > http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02880.html > > >> @@ -959,3 +966,7 @@ >> (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) >> >> (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) >> + >> +(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) >> +(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) >> + > > Superflous trailing blank line. > >> diff --git a/gcc/testsuite/gcc.target/aarch64/aes.c >> b/gcc/testsuite/gcc.target/aarch64/aes.c >> new file mode 100644 >> index 0000000..82665fa >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/aarch64/aes.c >> @@ -0,0 +1,40 @@ >> + >> +/* { dg-do compile } */ >> +/* { dg-options "-march=armv8-a+crypto" } */ >> + >> +#include "arm_neon.h" >> + >> +uint8x16_t >> +test_vaeseq_u8 (uint8x16_t data, uint8x16_t key) >> +{ >> + return vaeseq_u8 (data, key); >> +} >> + >> +/* { dg-final { scan-assembler "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" } } > > Use scan-assembler-times 1 instead please. Thanks for the review. Here is an improved patch. Tested on aarch64-none-elf. OK for trunk? Thanks Tejas. 2013-12-18 Tejas Belagod gcc/ * config/aarch64/aarch64-simd-builtins.def: Update builtins table. * config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers, TYPES_BINOPU): New. * config/aarch64/aarch64-simd.md (aarch64_crypto_aesv16qi, aarch64_crypto_aesv16qi): New. * config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8, vaesimcq_u8): New. * config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC, UNSPEC_AESIMC): New. (CRYPTO_AES, CRYPTO_AESMC): New int iterators. (aes_op, aesmc_op): New int attributes. testsuite/ * gcc.target/aarch64/aes_1.c: New. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 1bc3cc5..00a33ce 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -142,6 +142,10 @@ static enum aarch64_type_qualifiers aarch64_types_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none }; #define TYPES_UNOP (aarch64_types_unop_qualifiers) +static enum aarch64_type_qualifiers +aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned }; +#define TYPES_UNOPU (aarch64_types_unopu_qualifiers) #define TYPES_CREATE (aarch64_types_unop_qualifiers) #define TYPES_REINTERP (aarch64_types_unop_qualifiers) static enum aarch64_type_qualifiers @@ -149,6 +153,10 @@ aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_maybe_immediate }; #define TYPES_BINOP (aarch64_types_binop_qualifiers) static enum aarch64_type_qualifiers +aarch64_types_binopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned }; +#define TYPES_BINOPU (aarch64_types_binopu_qualifiers) +static enum aarch64_type_qualifiers aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; #define TYPES_TERNOP (aarch64_types_ternop_qualifiers) diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 1dc3c1f..6b72e8f 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -367,3 +367,8 @@ BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0) BUILTIN_VALLDIF (BSL_S, simd_bsl, 0) + /* Implemented by aarch64_crypto_aes. */ + VAR1 (BINOPU, crypto_aese, 0, v16qi) + VAR1 (BINOPU, crypto_aesd, 0, v16qi) + VAR1 (UNOPU, crypto_aesmc, 0, v16qi) + VAR1 (UNOPU, crypto_aesimc, 0, v16qi) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 158b3dc..f8c204f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4074,3 +4074,25 @@ (gen_aarch64_get_lane (operands[0], operands[1], operands[2])); DONE; }) + +;; aes + +(define_insn "aarch64_crypto_aesv16qi" + [(set (match_operand:V16QI 0 "register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0") + (match_operand:V16QI 2 "register_operand" "w")] + CRYPTO_AES))] + "TARGET_SIMD && TARGET_CRYPTO" + "aes\\t%0.16b, %2.16b" + [(set_attr "type" "crypto_aes")] +) + +(define_insn "aarch64_crypto_aesv16qi" + [(set (match_operand:V16QI 0 "register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "w")] + CRYPTO_AESMC))] + "TARGET_SIMD && TARGET_CRYPTO" + "aes\\t%0.16b, %1.16b" + [(set_attr "type" "crypto_aes")] +) + diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 03549bd..6cfea43 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -15575,6 +15575,36 @@ vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c) return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c); } +#ifdef __ARM_FEATURE_CRYPTO + +/* vaes */ + +static __inline uint8x16_t +vaeseq_u8 (uint8x16_t data, uint8x16_t key) +{ + return __builtin_aarch64_crypto_aesev16qi_uuu (data, key); +} + +static __inline uint8x16_t +vaesdq_u8 (uint8x16_t data, uint8x16_t key) +{ + return __builtin_aarch64_crypto_aesdv16qi_uuu (data, key); +} + +static __inline uint8x16_t +vaesmcq_u8 (uint8x16_t data) +{ + return __builtin_aarch64_crypto_aesmcv16qi_uu (data); +} + +static __inline uint8x16_t +vaesimcq_u8 (uint8x16_t data) +{ + return __builtin_aarch64_crypto_aesimcv16qi_uu (data); +} + +#endif + /* vcage */ __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 43279ad..eeab8e9 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -267,6 +267,10 @@ UNSPEC_UZP2 ; Used in vector permute patterns. UNSPEC_TRN1 ; Used in vector permute patterns. UNSPEC_TRN2 ; Used in vector permute patterns. + UNSPEC_AESE ; Used in aarch64-simd.md. + UNSPEC_AESD ; Used in aarch64-simd.md. + UNSPEC_AESMC ; Used in aarch64-simd.md. + UNSPEC_AESIMC ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------- @@ -848,6 +852,9 @@ (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) +(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) +(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) + ;; ------------------------------------------------------------------- ;; Int Iterators Attributes. ;; ------------------------------------------------------------------- @@ -964,3 +971,6 @@ (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) + +(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) +(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) diff --git a/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc/testsuite/gcc.target/aarch64/aes_1.c new file mode 100644 index 0000000..5fa6137 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aes_1.c @@ -0,0 +1,40 @@ + +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+crypto" } */ + +#include "arm_neon.h" + +uint8x16_t +test_vaeseq_u8 (uint8x16_t data, uint8x16_t key) +{ + return vaeseq_u8 (data, key); +} + +/* { dg-final { scan-assembler-times "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + +uint8x16_t +test_vaesdq_u8 (uint8x16_t data, uint8x16_t key) +{ + return vaesdq_u8 (data, key); +} + +/* { dg-final { scan-assembler-times "aesd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + +uint8x16_t +test_vaesmcq_u8 (uint8x16_t data) +{ + return vaesmcq_u8 (data); +} + +/* { dg-final { scan-assembler-times "aesmc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + +uint8x16_t +test_vaesimcq_u8 (uint8x16_t data) +{ + return vaesimcq_u8 (data); +} + +/* { dg-final { scan-assembler-times "aesimc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + + +/* { dg-final { cleanup-saved-temps } } */