From patchwork Thu Nov 21 13:43:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 293153 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CC5332C00B9 for ; Fri, 22 Nov 2013 00:45:38 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=dpgSUOVQwrka6jxKaVgmgaGlTbzwVgeZOmCGha5IjWP8xw CQ9AWczO9uu5LVP8YwSODKaywuHVIlPP0VvQAOOq4EpxdKpQEYR4MDfFknlJHxF8 vuMiOVpkjlZotBAXeP0Ivd8buB9agKubX/ZbrgIKTJOPt/QxBJnkqxa+d6ikA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=9dg+yLfan45PH1AErEhSuTqac98=; b=yr4hSxD/uUMPHgtxanCA mSDyo/wcfz+YfzOOB4fp1Kn2wLKToxF3+R4pVVQKywfUJTvlTkgsls/KOSRKVgME V0qRhSnVsk68fjjcV4HakRPnQG+xKHmSRZIxmBaJmvpk9JVTr6/eGgN5oL7RSYSq XjBb7kkAHtSaCuA7UldoeKQ= Received: (qmail 3457 invoked by alias); 21 Nov 2013 13:44:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3418 invoked by uid 89); 21 Nov 2013 13:44:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=AWL, BAYES_50, RDNS_NONE, SPF_PASS, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: service87.mimecast.com Received: from Unknown (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 21 Nov 2013 13:43:36 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 21 Nov 2013 13:43:28 +0000 Received: from [10.1.203.80] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 21 Nov 2013 13:43:26 +0000 Message-ID: <528E0DFE.1090907@arm.com> Date: Thu, 21 Nov 2013 13:43:26 +0000 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch 2/4] Conform vector implementation to ABI -- lane set and get. X-MC-Unique: 113112113432802801 X-IsSubscribed: yes Hi, This patch fixes up the lane access patterns to be symmetric to the order in which vectors are stored in registers. Tested for aarch64-none-elf and aarch64_be-none-elf. OK for trunk? Thanks, Tejas Belagod ARM. 2013-11-21 Tejas Belagod gcc/ * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set): Adjust for big-endian element order. (aarch64_simd_vec_setv2di): Likewise. (*aarch64_get_lane_extend, *aarch64_get_lane_zero_extendsi, aarch64_get_lane): Likewise. (vec_extract): Expand using aarch64_get_lane. * config/aarch64/aarch64.h (ENDIAN_LANE_N): New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b9ebdf5..b4a0a5b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -428,9 +428,19 @@ (match_operand:VQ_S 3 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "i,i")))] "TARGET_SIMD" - "@ - ins\t%0.[%p2], %w1 - ins\\t%0.[%p2], %1.[0]" + { + int elt = ENDIAN_LANE_N (mode, exact_log2 (INTVAL (operands[2]))); + operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); + switch (which_alternative) + { + case 0: + return "ins\\t%0.[%p2], %w1"; + case 1: + return "ins\\t%0.[%p2], %1.[0]"; + default: + gcc_unreachable (); + } + } [(set_attr "type" "neon_from_gp, neon_ins")] ) @@ -692,9 +702,19 @@ (match_operand:V2DI 3 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "i,i")))] "TARGET_SIMD" - "@ - ins\t%0.d[%p2], %1 - ins\\t%0.d[%p2], %1.d[0]" + { + int elt = ENDIAN_LANE_N (V2DImode, exact_log2 (INTVAL (operands[2]))); + operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); + switch (which_alternative) + { + case 0: + return "ins\\t%0.d[%p2], %1"; + case 1: + return "ins\\t%0.d[%p2], %1.d[0]"; + default: + gcc_unreachable (); + } + } [(set_attr "type" "neon_from_gp, neon_ins_q")] ) @@ -719,7 +739,12 @@ (match_operand:VDQF 3 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" - "ins\t%0.[%p2], %1.[0]"; + { + int elt = ENDIAN_LANE_N (mode, exact_log2 (INTVAL (operands[2]))); + + operands[2] = GEN_INT ((HOST_WIDE_INT)1 << elt); + return "ins\t%0.[%p2], %1.[0]"; + } [(set_attr "type" "neon_ins")] ) @@ -2022,7 +2047,10 @@ (match_operand:VDQQH 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] "TARGET_SIMD" - "smov\\t%0, %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "smov\\t%0, %1.[%2]"; + } [(set_attr "type" "neon_to_gp")] ) @@ -2033,22 +2061,36 @@ (match_operand:VDQQH 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] "TARGET_SIMD" - "umov\\t%w0, %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "umov\\t%w0, %1.[%2]"; + } [(set_attr "type" "neon_to_gp")] ) ;; Lane extraction of a value, neither sign nor zero extension ;; is guaranteed so upper bits should be considered undefined. (define_insn "aarch64_get_lane" - [(set (match_operand: 0 "register_operand" "=r, w") + [(set (match_operand: 0 "register_operand" "=r, w, Utv") (vec_select: - (match_operand:VALL 1 "register_operand" "w, w") - (parallel [(match_operand:SI 2 "immediate_operand" "i, i")])))] + (match_operand:VALL 1 "register_operand" "w, w, w") + (parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))] "TARGET_SIMD" - "@ - umov\\t%0, %1.[%2] - dup\\t%0, %1.[%2]" - [(set_attr "type" "neon_to_gp, neon_dup")] + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + switch (which_alternative) + { + case 0: + return "umov\\t%0, %1.[%2]"; + case 1: + return "dup\\t%0, %1.[%2]"; + case 2: + return "st1\\t{%1.}[%2], %0"; + default: + gcc_unreachable (); + } + } + [(set_attr "type" "neon_to_gp, neon_dup, neon_store1_one_lane")] ) (define_expand "aarch64_get_lanedi" @@ -4028,16 +4070,13 @@ ;; Standard pattern name vec_extract. -(define_insn "vec_extract" - [(set (match_operand: 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv") - (vec_select: - (match_operand:VALL 1 "register_operand" "w, w, w") - (parallel [(match_operand:SI 2 "immediate_operand" "i,i,i")])))] +(define_expand "vec_extract" + [(match_operand: 0 "aarch64_simd_nonimmediate_operand" "") + (match_operand:VALL 1 "register_operand" "") + (match_operand:SI 2 "immediate_operand" "")] "TARGET_SIMD" - "@ - umov\\t%0, %1.[%2] - dup\\t%0, %1.[%2] - st1\\t{%1.}[%2], %0" - [(set_attr "type" "neon_to_gp, neon_dup, neon_store1_one_lane")] -) - +{ + emit_insn + (gen_aarch64_get_lane (operands[0], operands[1], operands[2])); + DONE; +}) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 8b55a7b..ab5e45c 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -854,4 +854,7 @@ extern enum aarch64_code_model aarch64_cmodel; ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode) +#define ENDIAN_LANE_N(mode, n) \ + (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) + #endif /* GCC_AARCH64_H */