From patchwork Fri Jul 12 10:25:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 258735 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 51FF82C034C for ; Fri, 12 Jul 2013 20:25:20 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=Mu1mXhVx1tInjV9NUyZtxmOPKnscC84TXipKIs3tfIUNA5 Mf7yWyLjwxceJgi329iXiSVC0aLxJt1OIbBM/iWoW8vl7CPertaeqcbL9z07ux2a WG6O6rlFCr+2Q60u8ufUoynrFoF8G4zhbj/xzo4uHjpG9lJHTZqlvSpZxo+Hw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=YI9iRjtUxA5DwMTyY6plZu0i+uM=; b=bdDG6P1VVhl4vGTHVZ5+ rq8TekVWFbRm4MDbzCMuWQdR6+KykQMbfY29mTREyOmSqAg0u48rNZ1lgflYovb/ KZgdNtxoUO15Lzr8f/T8L5Usf8AFij+S/s90PSf2uiCZxBH9llJHvoUgDx8A7PRG bDxM1ojf1O8r8atPbTal8s0= Received: (qmail 22694 invoked by alias); 12 Jul 2013 10:25:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22648 invoked by uid 89); 12 Jul 2013 10:25:07 -0000 X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS, TW_MV, TW_XF autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 12 Jul 2013 10:25:06 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 12 Jul 2013 11:25:03 +0100 Received: from [10.1.203.80] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 12 Jul 2013 11:25:00 +0100 Message-ID: <51DFD97C.8070608@arm.com> Date: Fri, 12 Jul 2013 11:25:00 +0100 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch, AArch64] Support AdvSIMD MOVI / MVNI shifting ones variant. X-MC-Unique: 113071211250300201 X-Virus-Found: No Hi, This patch adds support for AdvSIMD MOVI/MVNI Vd., #imm8, MSL, #amount. OK? Thanks, Tejas Belagod ARM. Changelog: 2013-07-12 Tejas Belagod gcc/ * config/aarch64/aarch64-protos.h (aarch64_simd_immediate_valid_for_move): Remove. * config/aarch64/aarch64.c (simd_immediate_info): New member. (aarch64_simd_valid_immediate): Recognize idioms for shifting ones cases. (aarch64_output_simd_mov_immediate): Print the correct shift specifier. testsuite/ * gcc.target/aarch64/vect-movi.c: New. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index e5ae556..c4ea1fa 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -181,9 +181,6 @@ int aarch64_asm_preferred_eh_data_format (int, int); int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode); int aarch64_hard_regno_nregs (unsigned, enum machine_mode); int aarch64_simd_attr_length_move (rtx); -int aarch64_simd_immediate_valid_for_move (rtx, enum machine_mode, rtx *, - int *, unsigned char *, int *, - int *); int aarch64_uxt_size (int, HOST_WIDE_INT); rtx aarch64_final_eh_return_addr (void); rtx aarch64_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 94db053..9fa18b6 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -93,6 +93,7 @@ struct simd_immediate_info int shift; int element_width; bool mvn; + bool msl; }; /* The current code model. */ @@ -6319,16 +6320,16 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1], 8, 1); CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] - && bytes[i + 2] == 0 && bytes[i + 3] == 0, 0, 0); + && bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0); CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] - && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 0, 1); + && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1); CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff - && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 0, 0); + && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0); CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 - && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 0, 1); + && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1); CHECK (1, 8, 16, bytes[i] == bytes[0], 0, 0); @@ -6337,12 +6338,7 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, } while (0); - /* TODO: Currently the assembler cannot handle types 12 to 15. - And there is no way to specify cmode through the compiler. - Disable them till there is support in the assembler. */ - if (immtype == -1 - || (immtype >= 12 && immtype <= 15) - || immtype == 18) + if (immtype == -1) return false; if (info) @@ -6353,6 +6349,9 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, unsigned HOST_WIDE_INT imm = 0; + if (immtype >= 12 && immtype <= 15) + info->msl = true; + /* Un-invert bytes of recognized vector, if necessary. */ if (invmask != 0) for (i = 0; i < idx; i++) @@ -7285,10 +7284,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector, bool is_valid; static char templ[40]; const char *mnemonic; + const char *shift_op; unsigned int lane_count = 0; char element_char; - struct simd_immediate_info info; + struct simd_immediate_info info = { NULL_RTX, 0, 0, false, false }; /* This will return true to show const_vector is legal for use as either a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will @@ -7324,14 +7324,15 @@ aarch64_output_simd_mov_immediate (rtx const_vector, } mnemonic = info.mvn ? "mvni" : "movi"; + shift_op = info.msl ? "msl" : "lsl"; if (lane_count == 1) snprintf (templ, sizeof (templ), "%s\t%%d0, " HOST_WIDE_INT_PRINT_HEX, mnemonic, UINTVAL (info.value)); else if (info.shift) snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX - ", lsl %d", mnemonic, lane_count, element_char, - UINTVAL (info.value), info.shift); + ", %s %d", mnemonic, lane_count, element_char, + UINTVAL (info.value), shift_op, info.shift); else snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX, mnemonic, lane_count, element_char, UINTVAL (info.value)); diff --git a/gcc/testsuite/gcc.target/aarch64/vect-movi.c b/gcc/testsuite/gcc.target/aarch64/vect-movi.c new file mode 100644 index 0000000..59a0bd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-movi.c @@ -0,0 +1,74 @@ +/* { dg-do run } */ +/* { dg-options "-O3 --save-temps -fno-inline" } */ + +extern void abort (void); + +#define N 16 + +static void +movi_msl8 (int *__restrict a) +{ + int i; + + /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */ + for (i = 0; i < N; i++) + a[i] = 0xabff; +} + +static void +movi_msl16 (int *__restrict a) +{ + int i; + + /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */ + for (i = 0; i < N; i++) + a[i] = 0xabffff; +} + +static void +mvni_msl8 (int *__restrict a) +{ + int i; + + /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */ + for (i = 0; i < N; i++) + a[i] = 0xffff5400; +} + +static void +mvni_msl16 (int *__restrict a) +{ + int i; + + /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */ + for (i = 0; i < N; i++) + a[i] = 0xff540000; +} + +int +main (void) +{ + int a[N] = { 0 }; + int i; + +#define CHECK_ARRAY(a, val) \ + for (i = 0; i < N; i++) \ + if (a[i] != val) \ + abort (); + + movi_msl8 (a); + CHECK_ARRAY (a, 0xabff); + + movi_msl16 (a); + CHECK_ARRAY (a, 0xabffff); + + mvni_msl8 (a); + CHECK_ARRAY (a, 0xffff5400); + + mvni_msl16 (a); + CHECK_ARRAY (a, 0xff540000); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */