From patchwork Thu Aug 16 00:01:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandra Loosemore X-Patchwork-Id: 177883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 5A8A92C0093 for ; Thu, 16 Aug 2012 10:01:57 +1000 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Received:Message-ID:Date:From:User-Agent:MIME-Version:To:Subject:References:In-Reply-To:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=r1yW8DZ8cJireotvP4aYvS2g/y6uFoGVkT6q/VRDC9yU7DunnX4wocQndNca/T sPLnfemXhdV9hGywzPk2a7zAc+RJ8vDrSkbLybAcFx47CnteY9bV6PZZUWXRpQlt HwC+HHg1MNQ1vpMG8m/cwBsJocWZf6vm0rck2/otmSVHQ=; Received: (qmail 26509 invoked by alias); 16 Aug 2012 00:01:49 -0000 Received: (qmail 26284 invoked by uid 22791); 16 Aug 2012 00:01:35 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=AWL, BAYES_50, KHOP_RCVD_UNTRUST, KHOP_THREADED, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL, TW_TR X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 16 Aug 2012 00:01:17 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1T1nWV-0007Qh-Jf from Sandra_Loosemore@mentor.com ; Wed, 15 Aug 2012 17:01:15 -0700 Received: from SVR-ORW-FEM-04.mgc.mentorg.com ([147.34.97.41]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 15 Aug 2012 17:01:14 -0700 Received: from [IPv6:::1] (147.34.91.1) by svr-orw-fem-04.mgc.mentorg.com (147.34.97.41) with Microsoft SMTP Server id 14.1.289.1; Wed, 15 Aug 2012 17:01:13 -0700 Message-ID: <502C3846.8060407@codesourcery.com> Date: Wed, 15 Aug 2012 18:01:10 -0600 From: Sandra Loosemore User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101208 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: , Subject: Re: [PATCH, MIPS] DSP ALU scheduling References: <501B0483.6050404@codesourcery.com> <87wr1elq1u.fsf@talisman.home> In-Reply-To: <87wr1elq1u.fsf@talisman.home> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 08/04/2012 07:55 AM, Richard Sandiford wrote: > Sandra Loosemore writes: >> This is another patch that has been present in our local source base for some >> years now. It originally came from MIPS; I've verified that we have legal >> permission to contribute it to the FSF. >> >> The 74k.md parts of this patch depend on the not-yet-reviewed "74k madd scheduler >> tweaks" patch I posted the other day: >> >> http://gcc.gnu.org/ml/gcc-patches/2012-08/msg00062.html >> >> Assuming that one gets approved, is this patch OK for mainline? > > OK with: > >> +/* DSP ALU can bypass data with no delays for the following pairs. */ >> +enum insn_code dspalu_bypass_table[][2] = >> +{ >> + {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc}, >> + {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb}, >> + {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb}, >> + {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb}, >> + {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph}, >> + {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph}, >> + {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph}, >> + {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv} >> +}; >> + >> +int >> +mips_dspalu_bypass_p (rtx out_insn, rtx in_insn) >> +{ >> + int i; >> + int num_bypass = (sizeof (dspalu_bypass_table) >> + / (2 * sizeof (enum insn_code))); > > this changed to ARRAY_SIZE (dspalu_bypass_table); Here's the version I've checked in. In addition to the change above, I implemented the suggestion here http://gcc.gnu.org/ml/gcc-patches/2012-08/msg00463.html to remove the uses of mips_mult_madd_chain_bypass_p. -Sandra 2012-08-15 Sandra Loosemore Maxim Kuvyrkov Julian Brown MIPS Technologies, Inc. gcc/ * config/mips/mips.md (dspmac, dspmacsat, accext, accmod, dspalu) (dspalusat): Add insn types. * config/mips/mips-dsp.md (add3) (mips_add_s_) (sub3, mips_sub_s_, mips_addsc) (mips_addwc, mips_modsub, mips_raddu_w_qb, mips_absq_s_) (mips_precrq_qb_ph, mips_precrq_ph_w, mips_precrq_rs_ph_w) (mips_precrqu_s_qb_ph, mips_preceq_w_phl, mips_preceq_w_phr) (mips_precequ_ph_qbl, mips_precequ_ph_qbr, mips_precequ_ph_qbla) (mips_precequ_ph_qbra, mips_preceu_ph_qbl, mips_preceu_ph_qbr) (mips_preceu_ph_qbla, mips_preceu_ph_qbra, mips_shll_) (mips_shll_s_, mips_shll_s_, mips_shrl_qb) (mips_shra_ph, mips_shra_r_, mips_bitrev, mips_insv) (mips_repl_qb, mips_repl_ph) (mips_cmp_eq_) (mips_cmp_lt_) (mips_cmp_le_, mips_cmpgu_eq_qb) (mips_cmpgu_lt_qb, mips_cmpgu_le_qb, mips_pick_) (mips_packrl_ph, mips_wrdsp, mips_rddsp): Change type to dspalu. (mips_dpau_h_qbl, mips_dpau_h_qbr, mips_dpsu_h_qbl, mips_dpsu_h_qbr) (mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph) (mips_maq_s_w_phl, mips_maq_s_w_phr, mips_maq_sa_w_phr): Set type to dspmac. (mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_sa_w_phl): Set type to dspmacsat. (mips_extr_w, mips_extr_r_w, mips_extr_rs_w, mips_extp, mips_extpdp): Set type to accext. (mips_shilo, mips_mthlip): Set type to accmod. * config/mips/mips-dspr2.md (mips_absq_s_qb, mips_addu_s_ph) (mips_adduh_r_qb): Set type to dspalusat. (mips_addu_ph, mips_adduh_qb, mips_append, mips_balign) (mips_cmpgdu_eq_qb, mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb) (mips_precr_qb_ph, mips_precr_sra_ph_w, mips_precr_sra_r_ph_w) (mips_prepend, mips_shra_qb, mips_shra_r_qb, mips_shrl_ph) (mips_subu_ph, mips_subuh_qb, mips_subuh_r_qb, mips_addqh_ph) (mips_addqh_r_ph, mips_addqh_w, mips_addqh_r_w, mips_subqh_ph) (mips_subqh_r_ph, mips_subqh_w, mips_subqh_r_w): Set type to dspalu. (mips_dpa_w_ph, mips_dps_w_ph, mips_mulsa_w_ph, mips_dpax_w_ph) (mips_dpsx_w_ph, mips_dpaqx_s_w_ph, mips_dpsqx_s_w_ph): Set type to dspmac. Set accum_in attribute. (mips_subu_s_ph): Set type to dspalusat. (mips_dpaqx_sa_w_ph, mips_dpsqx_sa_w_ph): Set type to dspmacsat. Set accum_in attribute. * config/mips/mips-protos.h (mips_dspalu_bypass_p): Add prototype. * config/mips/mips.c (dspalu_bypass_table): New. (mips_dspalu_bypass_p): New. * config/mips/24k.md (r24k_dsp_alu, r24k_dsp_mac, r24k_dsp_mac_sat) (r24k_dsp_acc_ext, r24k_dsp_acc_mod): New insn reservations. (r24k_int_mult, r24k_int_mthilo, r24k_dsp_mac, r24k_dsp_mac_sat) (r24k_dsp_acc_ext, r24k_dsp_acc_mod, r24k_dsp_alu): New bypasses. * config/mips/74k.md (r74k_dsp_alu, r74k_dsp_alu_sat, r74k_dsp_mac) (r74k_dsp_mac_sat, r74k_dsp_acc_ext, r74k_dsp_acc_mod): New insn reservations. (r74k_dsp_mac, r74k_dsp_mac_sat, r74k_int_mult, r74k_int_mul3) (r74k_dsp_mac, r74k_dsp_mac_sat): New bypasses. Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md (revision 190415) +++ gcc/config/mips/mips.md (working copy) @@ -328,6 +328,12 @@ ;; frsqrt floating point reciprocal square root ;; frsqrt1 floating point reciprocal square root step1 ;; frsqrt2 floating point reciprocal square root step2 +;; dspmac DSP MAC instructions not saturating the accumulator +;; dspmacsat DSP MAC instructions that saturate the accumulator +;; accext DSP accumulator extract instructions +;; accmod DSP accumulator modify instructions +;; dspalu DSP ALU instructions not saturating the result +;; dspalusat DSP ALU instructions that saturate the result ;; multi multiword sequence (or user asm statements) ;; atomic atomic memory update instruction ;; syncloop memory atomic operation implemented as a sync loop @@ -338,7 +344,8 @@ prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, - frsqrt,frsqrt1,frsqrt2,multi,atomic,syncloop,nop,ghost" + frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, + multi,atomic,syncloop,nop,ghost" (cond [(eq_attr "jal" "!unset") (const_string "call") (eq_attr "got" "load") (const_string "load") Index: gcc/config/mips/mips-dsp.md =================================================================== --- gcc/config/mips/mips-dsp.md (revision 190415) +++ gcc/config/mips/mips-dsp.md (working copy) @@ -135,7 +135,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] "ISA_HAS_DSP" "add.\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_add_s_" @@ -148,7 +148,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] "ISA_HAS_DSP" "add_s.\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) ;; SUBQ* @@ -161,7 +161,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] "ISA_HAS_DSP" "sub.\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_sub_s_" @@ -174,7 +174,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] "ISA_HAS_DSP" "sub_s.\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) ;; ADDSC @@ -188,7 +188,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] "ISA_HAS_DSP" "addsc\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; ADDWC @@ -203,7 +203,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] "ISA_HAS_DSP" "addwc\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; MODSUB @@ -214,7 +214,7 @@ UNSPEC_MODSUB))] "ISA_HAS_DSP" "modsub\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; RADDU* @@ -224,7 +224,7 @@ UNSPEC_RADDU_W_QB))] "ISA_HAS_DSP" "raddu.w.qb\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; ABSQ* @@ -237,7 +237,7 @@ (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] "ISA_HAS_DSP" "absq_s.\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) ;; PRECRQ* @@ -248,7 +248,7 @@ UNSPEC_PRECRQ_QB_PH))] "ISA_HAS_DSP" "precrq.qb.ph\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precrq_ph_w" @@ -258,7 +258,7 @@ UNSPEC_PRECRQ_PH_W))] "ISA_HAS_DSP" "precrq.ph.w\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precrq_rs_ph_w" @@ -272,7 +272,7 @@ UNSPEC_PRECRQ_RS_PH_W))])] "ISA_HAS_DSP" "precrq_rs.ph.w\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; PRECRQU* @@ -287,7 +287,7 @@ UNSPEC_PRECRQU_S_QB_PH))])] "ISA_HAS_DSP" "precrqu_s.qb.ph\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) ;; PRECEQ* @@ -297,7 +297,7 @@ UNSPEC_PRECEQ_W_PHL))] "ISA_HAS_DSP" "preceq.w.phl\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_preceq_w_phr" @@ -306,7 +306,7 @@ UNSPEC_PRECEQ_W_PHR))] "ISA_HAS_DSP" "preceq.w.phr\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; PRECEQU* @@ -316,7 +316,7 @@ UNSPEC_PRECEQU_PH_QBL))] "ISA_HAS_DSP" "precequ.ph.qbl\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precequ_ph_qbr" @@ -325,7 +325,7 @@ UNSPEC_PRECEQU_PH_QBR))] "ISA_HAS_DSP" "precequ.ph.qbr\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precequ_ph_qbla" @@ -334,7 +334,7 @@ UNSPEC_PRECEQU_PH_QBLA))] "ISA_HAS_DSP" "precequ.ph.qbla\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precequ_ph_qbra" @@ -343,7 +343,7 @@ UNSPEC_PRECEQU_PH_QBRA))] "ISA_HAS_DSP" "precequ.ph.qbra\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; PRECEU* @@ -353,7 +353,7 @@ UNSPEC_PRECEU_PH_QBL))] "ISA_HAS_DSP" "preceu.ph.qbl\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_preceu_ph_qbr" @@ -362,7 +362,7 @@ UNSPEC_PRECEU_PH_QBR))] "ISA_HAS_DSP" "preceu.ph.qbr\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_preceu_ph_qbla" @@ -371,7 +371,7 @@ UNSPEC_PRECEU_PH_QBLA))] "ISA_HAS_DSP" "preceu.ph.qbla\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_preceu_ph_qbra" @@ -380,7 +380,7 @@ UNSPEC_PRECEU_PH_QBRA))] "ISA_HAS_DSP" "preceu.ph.qbra\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; Table 2-2. MIPS DSP ASE Instructions: Shift @@ -404,7 +404,7 @@ } return "shllv.\t%0,%1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_shll_s_" @@ -426,7 +426,7 @@ } return "shllv_s.\t%0,%1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) ;; SHRL* @@ -445,7 +445,7 @@ } return "shrlv.qb\t%0,%1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; SHRA* @@ -464,7 +464,7 @@ } return "shrav.ph\t%0,%1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_shra_r_" @@ -483,7 +483,7 @@ } return "shrav_r.\t%0,%1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; Table 2-3. MIPS DSP ASE Instructions: Multiply @@ -569,7 +569,7 @@ UNSPEC_DPAU_H_QBL))] "ISA_HAS_DSP && !TARGET_64BIT" "dpau.h.qbl\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) (define_insn "mips_dpau_h_qbr" @@ -580,7 +580,7 @@ UNSPEC_DPAU_H_QBR))] "ISA_HAS_DSP && !TARGET_64BIT" "dpau.h.qbr\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) ;; DPSU* @@ -592,7 +592,7 @@ UNSPEC_DPSU_H_QBL))] "ISA_HAS_DSP && !TARGET_64BIT" "dpsu.h.qbl\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) (define_insn "mips_dpsu_h_qbr" @@ -603,7 +603,7 @@ UNSPEC_DPSU_H_QBR))] "ISA_HAS_DSP && !TARGET_64BIT" "dpsu.h.qbr\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) ;; DPAQ* @@ -619,7 +619,7 @@ UNSPEC_DPAQ_S_W_PH))])] "ISA_HAS_DSP && !TARGET_64BIT" "dpaq_s.w.ph\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) ;; DPSQ* @@ -635,7 +635,7 @@ UNSPEC_DPSQ_S_W_PH))])] "ISA_HAS_DSP && !TARGET_64BIT" "dpsq_s.w.ph\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) ;; MULSAQ* @@ -651,7 +651,7 @@ UNSPEC_MULSAQ_S_W_PH))])] "ISA_HAS_DSP && !TARGET_64BIT" "mulsaq_s.w.ph\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) ;; DPAQ* @@ -667,7 +667,7 @@ UNSPEC_DPAQ_SA_L_W))])] "ISA_HAS_DSP && !TARGET_64BIT" "dpaq_sa.l.w\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmacsat") (set_attr "mode" "SI")]) ;; DPSQ* @@ -683,7 +683,7 @@ UNSPEC_DPSQ_SA_L_W))])] "ISA_HAS_DSP && !TARGET_64BIT" "dpsq_sa.l.w\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmacsat") (set_attr "mode" "SI")]) ;; MAQ* @@ -699,7 +699,7 @@ UNSPEC_MAQ_S_W_PHL))])] "ISA_HAS_DSP && !TARGET_64BIT" "maq_s.w.phl\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) (define_insn "mips_maq_s_w_phr" @@ -714,7 +714,7 @@ UNSPEC_MAQ_S_W_PHR))])] "ISA_HAS_DSP && !TARGET_64BIT" "maq_s.w.phr\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") (set_attr "mode" "SI")]) ;; MAQ_SA* @@ -730,7 +730,7 @@ UNSPEC_MAQ_SA_W_PHL))])] "ISA_HAS_DSP && !TARGET_64BIT" "maq_sa.w.phl\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmacsat") (set_attr "mode" "SI")]) (define_insn "mips_maq_sa_w_phr" @@ -745,7 +745,7 @@ UNSPEC_MAQ_SA_W_PHR))])] "ISA_HAS_DSP && !TARGET_64BIT" "maq_sa.w.phr\t%q0,%2,%3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmacsat") (set_attr "mode" "SI")]) ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation @@ -756,7 +756,7 @@ UNSPEC_BITREV))] "ISA_HAS_DSP" "bitrev\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; INSV @@ -769,7 +769,7 @@ UNSPEC_INSV))] "ISA_HAS_DSP" "insv\t%0,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; REPL* @@ -787,7 +787,7 @@ } return "replv.qb\t%0,%1"; } - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_repl_ph" @@ -798,7 +798,7 @@ "@ repl.ph\t%0,%1 replv.ph\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick @@ -811,7 +811,7 @@ UNSPEC_CMP_EQ))] "ISA_HAS_DSP" "cmp.eq.\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmp_lt_" @@ -822,7 +822,7 @@ UNSPEC_CMP_LT))] "ISA_HAS_DSP" "cmp.lt.\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmp_le_" @@ -833,7 +833,7 @@ UNSPEC_CMP_LE))] "ISA_HAS_DSP" "cmp.le.\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmpgu_eq_qb" @@ -843,7 +843,7 @@ UNSPEC_CMPGU_EQ_QB))] "ISA_HAS_DSP" "cmpgu.eq.qb\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmpgu_lt_qb" @@ -853,7 +853,7 @@ UNSPEC_CMPGU_LT_QB))] "ISA_HAS_DSP" "cmpgu.lt.qb\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmpgu_le_qb" @@ -863,7 +863,7 @@ UNSPEC_CMPGU_LE_QB))] "ISA_HAS_DSP" "cmpgu.le.qb\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; PICK* @@ -875,7 +875,7 @@ UNSPEC_PICK))] "ISA_HAS_DSP" "pick.\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; PACKRL* @@ -886,7 +886,7 @@ UNSPEC_PACKRL_PH))] "ISA_HAS_DSP" "packrl.ph\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access @@ -909,7 +909,7 @@ } return "extrv.w\t%0,%q1,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accext") (set_attr "mode" "SI")]) (define_insn "mips_extr_r_w" @@ -930,7 +930,7 @@ } return "extrv_r.w\t%0,%q1,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accext") (set_attr "mode" "SI")]) (define_insn "mips_extr_rs_w" @@ -951,7 +951,7 @@ } return "extrv_rs.w\t%0,%q1,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accext") (set_attr "mode" "SI")]) ;; EXTR*_S.H @@ -973,7 +973,7 @@ } return "extrv_s.h\t%0,%q1,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accext") (set_attr "mode" "SI")]) ;; EXTP* @@ -996,7 +996,7 @@ } return "extpv\t%0,%q1,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accext") (set_attr "mode" "SI")]) (define_insn "mips_extpdp" @@ -1021,7 +1021,7 @@ } return "extpdpv\t%0,%q1,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accext") (set_attr "mode" "SI")]) ;; SHILO* @@ -1040,7 +1040,7 @@ } return "shilov\t%q0,%2"; } - [(set_attr "type" "mflo") + [(set_attr "type" "accmod") (set_attr "mode" "SI")]) ;; MTHLIP* @@ -1056,7 +1056,7 @@ (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] "ISA_HAS_DSP && !TARGET_64BIT" "mthlip\t%2,%q0" - [(set_attr "type" "mflo") + [(set_attr "type" "accmod") (set_attr "mode" "SI")]) ;; WRDSP @@ -1078,7 +1078,7 @@ (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] "ISA_HAS_DSP" "wrdsp\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; RDDSP @@ -1094,7 +1094,7 @@ UNSPEC_RDDSP))] "ISA_HAS_DSP" "rddsp\t%0,%1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load Index: gcc/config/mips/mips-dspr2.md =================================================================== --- gcc/config/mips/mips-dspr2.md (revision 190415) +++ gcc/config/mips/mips-dspr2.md (working copy) @@ -79,7 +79,7 @@ (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])] "ISA_HAS_DSPR2" "absq_s.qb\t%0,%z1" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) (define_insn "mips_addu_ph" @@ -91,7 +91,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])] "ISA_HAS_DSPR2" "addu.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_addu_s_ph" @@ -104,7 +104,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])] "ISA_HAS_DSPR2" "addu_s.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) (define_insn "mips_adduh_qb" @@ -114,7 +114,7 @@ UNSPEC_ADDUH_QB))] "ISA_HAS_DSPR2" "adduh.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_adduh_r_qb" @@ -124,7 +124,7 @@ UNSPEC_ADDUH_R_QB))] "ISA_HAS_DSPR2" "adduh_r.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) (define_insn "mips_append" @@ -139,7 +139,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & 31); return "append\t%0,%z2,%3"; } - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_balign" @@ -154,7 +154,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & 3); return "balign\t%0,%z2,%3"; } - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmpgdu_eq_qb" @@ -169,7 +169,7 @@ UNSPEC_CMPGDU_EQ_QB))])] "ISA_HAS_DSPR2" "cmpgdu.eq.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmpgdu_lt_qb" @@ -184,7 +184,7 @@ UNSPEC_CMPGDU_LT_QB))])] "ISA_HAS_DSPR2" "cmpgdu.lt.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_cmpgdu_le_qb" @@ -199,7 +199,7 @@ UNSPEC_CMPGDU_LE_QB))])] "ISA_HAS_DSPR2" "cmpgdu.le.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_dpa_w_ph" @@ -210,7 +210,8 @@ UNSPEC_DPA_W_PH))] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpa.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_dps_w_ph" @@ -221,7 +222,8 @@ UNSPEC_DPS_W_PH))] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dps.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mulv2hi3" @@ -301,7 +303,8 @@ UNSPEC_MULSA_W_PH))] "ISA_HAS_DSPR2 && !TARGET_64BIT" "mulsa.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_precr_qb_ph" @@ -311,7 +314,7 @@ UNSPEC_PRECR_QB_PH))] "ISA_HAS_DSPR2" "precr.qb.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precr_sra_ph_w" @@ -326,7 +329,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & 31); return "precr_sra.ph.w\t%0,%z2,%3"; } - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_precr_sra_r_ph_w" @@ -341,7 +344,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & 31); return "precr_sra_r.ph.w\t%0,%z2,%3"; } - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_prepend" @@ -356,7 +359,7 @@ operands[3] = GEN_INT (INTVAL (operands[3]) & 31); return "prepend\t%0,%z2,%3"; } - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_shra_qb" @@ -374,7 +377,7 @@ } return "shrav.qb\t%0,%z1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) @@ -393,7 +396,7 @@ } return "shrav_r.qb\t%0,%z1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_shrl_ph" @@ -411,7 +414,7 @@ } return "shrlv.ph\t%0,%z1,%2"; } - [(set_attr "type" "shift") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subu_ph" @@ -424,7 +427,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])] "ISA_HAS_DSPR2" "subu.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subu_s_ph" @@ -437,7 +440,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])] "ISA_HAS_DSPR2" "subu_s.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalusat") (set_attr "mode" "SI")]) (define_insn "mips_subuh_qb" @@ -447,7 +450,7 @@ UNSPEC_SUBUH_QB))] "ISA_HAS_DSPR2" "subuh.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subuh_r_qb" @@ -457,7 +460,7 @@ UNSPEC_SUBUH_R_QB))] "ISA_HAS_DSPR2" "subuh_r.qb\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_addqh_ph" @@ -467,7 +470,7 @@ UNSPEC_ADDQH_PH))] "ISA_HAS_DSPR2" "addqh.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_addqh_r_ph" @@ -477,7 +480,7 @@ UNSPEC_ADDQH_R_PH))] "ISA_HAS_DSPR2" "addqh_r.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_addqh_w" @@ -487,7 +490,7 @@ UNSPEC_ADDQH_W))] "ISA_HAS_DSPR2" "addqh.w\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_addqh_r_w" @@ -497,7 +500,7 @@ UNSPEC_ADDQH_R_W))] "ISA_HAS_DSPR2" "addqh_r.w\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subqh_ph" @@ -507,7 +510,7 @@ UNSPEC_SUBQH_PH))] "ISA_HAS_DSPR2" "subqh.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subqh_r_ph" @@ -517,7 +520,7 @@ UNSPEC_SUBQH_R_PH))] "ISA_HAS_DSPR2" "subqh_r.ph\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subqh_w" @@ -527,7 +530,7 @@ UNSPEC_SUBQH_W))] "ISA_HAS_DSPR2" "subqh.w\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_subqh_r_w" @@ -537,7 +540,7 @@ UNSPEC_SUBQH_R_W))] "ISA_HAS_DSPR2" "subqh_r.w\t%0,%z1,%z2" - [(set_attr "type" "arith") + [(set_attr "type" "dspalu") (set_attr "mode" "SI")]) (define_insn "mips_dpax_w_ph" @@ -548,7 +551,8 @@ UNSPEC_DPAX_W_PH))] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpax.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_dpsx_w_ph" @@ -559,7 +563,8 @@ UNSPEC_DPSX_W_PH))] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpsx.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_dpaqx_s_w_ph" @@ -574,7 +579,8 @@ UNSPEC_DPAQX_S_W_PH))])] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpaqx_s.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_dpaqx_sa_w_ph" @@ -589,7 +595,8 @@ UNSPEC_DPAQX_SA_W_PH))])] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpaqx_sa.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmacsat") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_dpsqx_s_w_ph" @@ -604,7 +611,8 @@ UNSPEC_DPSQX_S_W_PH))])] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpsqx_s.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmac") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) (define_insn "mips_dpsqx_sa_w_ph" @@ -619,5 +627,6 @@ UNSPEC_DPSQX_SA_W_PH))])] "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpsqx_sa.w.ph\t%q0,%z2,%z3" - [(set_attr "type" "imadd") + [(set_attr "type" "dspmacsat") + (set_attr "accum_in" "1") (set_attr "mode" "SI")]) Index: gcc/config/mips/mips-protos.h =================================================================== --- gcc/config/mips/mips-protos.h (revision 190415) +++ gcc/config/mips/mips-protos.h (working copy) @@ -298,6 +298,7 @@ extern const char *mips_output_division extern unsigned int mips_hard_regno_nregs (int, enum machine_mode); extern bool mips_linked_madd_p (rtx, rtx); extern bool mips_store_data_bypass_p (rtx, rtx); +extern int mips_dspalu_bypass_p (rtx, rtx); extern rtx mips_prefetch_cookie (rtx, rtx); extern const char *current_section_name (void); Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 190415) +++ gcc/config/mips/mips.c (working copy) @@ -8307,6 +8307,36 @@ mips_dwarf_register_span (rtx reg) return NULL_RTX; } +/* DSP ALU can bypass data with no delays for the following pairs. */ +enum insn_code dspalu_bypass_table[][2] = +{ + {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc}, + {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb}, + {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb}, + {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb}, + {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph}, + {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph}, + {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph}, + {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv} +}; + +int +mips_dspalu_bypass_p (rtx out_insn, rtx in_insn) +{ + int i; + int num_bypass = ARRAY_SIZE (dspalu_bypass_table); + enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn); + enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn); + + for (i = 0; i < num_bypass; i++) + { + if (out_icode == dspalu_bypass_table[i][0] + && in_icode == dspalu_bypass_table[i][1]) + return true; + } + + return false; +} /* Implement ASM_OUTPUT_ASCII. */ void Index: gcc/config/mips/24k.md =================================================================== --- gcc/config/mips/24k.md (revision 190415) +++ gcc/config/mips/24k.md (working copy) @@ -204,6 +204,101 @@ ;; -------------------------------------------------------------- +;; DSP instructions +;; -------------------------------------------------------------- + +;; absq, addq, addsc, addu, addwc, bitrev, cmp, cmpgu, cmpu, insv, modsub, +;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl, +;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp +(define_insn_reservation "r24k_dsp_alu" 2 + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (eq_attr "type" "dspalu,dspalusat")) + "r24k_iss+r24k_ixu_arith") + +;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq +(define_insn_reservation "r24k_dsp_mac" 1 + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (eq_attr "type" "dspmac")) + "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") + +;; dpaq_sa, dpsq_sa, maq_sa +(define_insn_reservation "r24k_dsp_mac_sat" 1 + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (eq_attr "type" "dspmacsat")) + "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") + +;; extp, extpdp, extpdpv, extpv, extr, extrv +(define_insn_reservation "r24k_dsp_acc_ext" 5 + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (eq_attr "type" "accext")) + "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") + +;; mthlip, shilo, shilov +(define_insn_reservation "r24k_dsp_acc_mod" 1 + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (eq_attr "type" "accmod")) + "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") + + +;; mult/madd->dsp_acc_ext : 4 cycles +;; mult/madd->dsp_acc_mod : 4 cycles +(define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_ext") +(define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_mod") + +;; mthilo->dsp_acc_ext : 4 cycles +;; mthilo->dsp_acc_ext : 4 cycles +(define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_ext") +(define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_mod") + +;; dsp_mac->next use : 1 cycles (default) +;; dsp_mac->dsp_acc_ext : 4 cycles +;; dsp_mac->dsp_acc_mod : 4 cycles +(define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_ext") +(define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_mod") + +;; dsp_mac_sat->next use : 1 cycles (default) +;; dsp_mac_sat->mult/madd : 2 cycles +;; dsp_mac_sat->dsp_mac : 2 cycles +;; dsp_mac_sat->dsp_mac_sat : 2 cycles +;; dsp_mac_sat->dsp_acc_ext : 4 cycles +;; dsp_mac_sat->dsp_acc_mod : 4 cycles +(define_bypass 2 "r24k_dsp_mac_sat" "r24k_int_mult") +(define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac") +(define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac_sat") +(define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_ext") +(define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_mod") + +;; dsp_acc_ext->next use : 5 cycles (default) +;; dsp_acc_ext->l/s base : 6 cycles +;; dsp_acc_ext->prefetch : 6 cycles +(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_load") +(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_store" + "!mips_store_data_bypass_p") +(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_prefetch") + +;; dsp_acc_mod->next use : 1 cycles (default) +;; dsp_acc_mod->mult/madd : 2 cycles +;; dsp_acc_mod->dsp_mac : 2 cycles +;; dsp_acc_mod->dsp_mac_sat : 2 cycles +;; dsp_acc_mod->dsp_acc_ext : 4 cycles +;; dsp_acc_mod->dsp_acc_mod : 4 cycles +(define_bypass 2 "r24k_dsp_acc_mod" "r24k_int_mult") +(define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac") +(define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac_sat") +(define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_ext") +(define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_mod") + +;; dspalu->next use : 2 cycles (default) +;; dspalu->l/s base : 3 cycles +;; dspalu->prefetch : 3 cycles +;; some pairs of dspalu (addsc/addwc, cmp/pick, wrdsp/insv) : 1 cycle +(define_bypass 3 "r24k_dsp_alu" "r24k_int_load") +(define_bypass 3 "r24k_dsp_alu" "r24k_int_store" "!mips_store_data_bypass_p") +(define_bypass 3 "r24k_dsp_alu" "r24k_int_prefetch") +(define_bypass 1 "r24k_dsp_alu" "r24k_dsp_alu" "mips_dspalu_bypass_p") + + +;; -------------------------------------------------------------- ;; Floating Point Instructions ;; -------------------------------------------------------------- Index: gcc/config/mips/74k.md =================================================================== --- gcc/config/mips/74k.md (revision 190415) +++ gcc/config/mips/74k.md (working copy) @@ -174,6 +174,88 @@ (define_bypass 1 "r74k_int_madd" "r74k_int_madd" "mips_linked_madd_p") + +;; -------------------------------------------------------------- +;; DSP instructions +;; -------------------------------------------------------------- + +;; Non-saturating insn have the same latency as normal ALU operations, +(define_insn_reservation "r74k_dsp_alu" 2 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspalu")) + "r74k_alu") + +;; Saturating insn takes an extra cycle. +(define_insn_reservation "r74k_dsp_alu_sat" 3 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspalusat")) + "r74k_alu") + +;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq +;; - delivers result to hi/lo in 6 cycle (bypass at M4) +(define_insn_reservation "r74k_dsp_mac" 6 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspmac")) + "r74k_alu+r74k_mul") + +;; dpaq_sa, dpsq_sa, maq_sa +;; - delivers result to hi/lo in 7 cycle (bypass at WB) +(define_insn_reservation "r74k_dsp_mac_sat" 7 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspmacsat")) + "r74k_alu+r74k_mul") + +;; extp, extpdp, extpdpv, extpv, extr, extrv +;; - same latency as "mul" +(define_insn_reservation "r74k_dsp_acc_ext" 7 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "accext")) + "r74k_alu+r74k_mul") + +;; mthlip, shilo, shilov +;; - same latency as "mul" +(define_insn_reservation "r74k_dsp_acc_mod" 7 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "accmod")) + "r74k_alu+r74k_mul") + +;; dspalu ->load/store base +;; dspalusat->load/store base +;; - we should never see these in real life. + +;; dsp_mac->dsp_mac : 1 cycles (repeat rate of 1) +;; dsp_mac->dsp_mac_sat : 1 cycles (repeat rate of 1) +(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac") +(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac_sat") + +;; dsp_mac_sat->dsp_mac_sat : 2 cycles (repeat rate of 2) +;; dsp_mac_sat->dsp_mac : 2 cycles (repeat rate of 2) +(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac_sat") +(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac") + +(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac") +(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac_sat") + +(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac" "mips_linked_madd_p") +(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac_sat" "mips_linked_madd_p") + +;; Assuming the following is true (bypass at M4) +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; dsp_mac->dsp_acc_ext : 4 cycles +;; dsp_mac->dsp_acc_mod : 4 cycles +(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_ext") +(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_mod") + +;; Assuming the following is true (bypass at WB) +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; dsp_mac_sat->dsp_acc_ext : 5 cycles +;; dsp_mac_sat->dsp_acc_mod : 5 cycles +(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_ext") +(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_mod") + + ;; -------------------------------------------------------------- ;; Floating Point Instructions ;; --------------------------------------------------------------