@@ -51,30 +51,24 @@
(each of which is overlaid on two S registers), although there are no
actual single-precision registers which correspond to D16-D31. */
#ifndef REGISTER_NAMES
-#define REGISTER_NAMES \
-{ \
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
- "cc", "sfp", "afp", \
- "mv0", "mv1", "mv2", "mv3", \
- "mv4", "mv5", "mv6", "mv7", \
- "mv8", "mv9", "mv10", "mv11", \
- "mv12", "mv13", "mv14", "mv15", \
- "wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "wr0", "wr1", "wr2", "wr3", \
- "wr4", "wr5", "wr6", "wr7", \
- "wr8", "wr9", "wr10", "wr11", \
- "wr12", "wr13", "wr14", "wr15", \
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
- "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
- "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
- "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
- "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
- "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
- "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
- "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
- "vfpcc" \
+#define REGISTER_NAMES \
+{ \
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+ "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc", \
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
+ "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
+ "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
+ "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
+ "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
+ "wr0", "wr1", "wr2", "wr3", \
+ "wr4", "wr5", "wr6", "wr7", \
+ "wr8", "wr9", "wr10", "wr11", \
+ "wr12", "wr13", "wr14", "wr15", \
+ "wcgr0", "wcgr1", "wcgr2", "wcgr3", \
+ "cc", "vfpcc", "sfp", "afp" \
}
#endif
@@ -91,117 +85,53 @@
{"v4", 7}, \
{"v5", 8}, \
{"v6", 9}, \
- {"rfp", 9}, /* Gcc used to call it this */ \
- {"sb", 9}, \
+ {"rfp", 9}, /* Historical. */ \
+ {"sb", 9}, /* Historical. */ \
{"v7", 10}, \
- {"r10", 10}, /* sl */ \
+ {"sl", 10}, /* Historical. */ \
{"r11", 11}, /* fp */ \
{"r12", 12}, /* ip */ \
{"r13", 13}, /* sp */ \
{"r14", 14}, /* lr */ \
- {"r15", 15}, /* pc */ \
- {"mvf0", 27}, \
- {"mvf1", 28}, \
- {"mvf2", 29}, \
- {"mvf3", 30}, \
- {"mvf4", 31}, \
- {"mvf5", 32}, \
- {"mvf6", 33}, \
- {"mvf7", 34}, \
- {"mvf8", 35}, \
- {"mvf9", 36}, \
- {"mvf10", 37}, \
- {"mvf11", 38}, \
- {"mvf12", 39}, \
- {"mvf13", 40}, \
- {"mvf14", 41}, \
- {"mvf15", 42}, \
- {"mvd0", 27}, \
- {"mvd1", 28}, \
- {"mvd2", 29}, \
- {"mvd3", 30}, \
- {"mvd4", 31}, \
- {"mvd5", 32}, \
- {"mvd6", 33}, \
- {"mvd7", 34}, \
- {"mvd8", 35}, \
- {"mvd9", 36}, \
- {"mvd10", 37}, \
- {"mvd11", 38}, \
- {"mvd12", 39}, \
- {"mvd13", 40}, \
- {"mvd14", 41}, \
- {"mvd15", 42}, \
- {"mvfx0", 27}, \
- {"mvfx1", 28}, \
- {"mvfx2", 29}, \
- {"mvfx3", 30}, \
- {"mvfx4", 31}, \
- {"mvfx5", 32}, \
- {"mvfx6", 33}, \
- {"mvfx7", 34}, \
- {"mvfx8", 35}, \
- {"mvfx9", 36}, \
- {"mvfx10", 37}, \
- {"mvfx11", 38}, \
- {"mvfx12", 39}, \
- {"mvfx13", 40}, \
- {"mvfx14", 41}, \
- {"mvfx15", 42}, \
- {"mvdx0", 27}, \
- {"mvdx1", 28}, \
- {"mvdx2", 29}, \
- {"mvdx3", 30}, \
- {"mvdx4", 31}, \
- {"mvdx5", 32}, \
- {"mvdx6", 33}, \
- {"mvdx7", 34}, \
- {"mvdx8", 35}, \
- {"mvdx9", 36}, \
- {"mvdx10", 37}, \
- {"mvdx11", 38}, \
- {"mvdx12", 39}, \
- {"mvdx13", 40}, \
- {"mvdx14", 41}, \
- {"mvdx15", 42} \
+ {"r15", 15} /* pc */ \
}
#endif
#ifndef OVERLAPPING_REGISTER_NAMES
#define OVERLAPPING_REGISTER_NAMES \
{ \
- {"d0", 63, 2}, \
- {"d1", 65, 2}, \
- {"d2", 67, 2}, \
- {"d3", 69, 2}, \
- {"d4", 71, 2}, \
- {"d5", 73, 2}, \
- {"d6", 75, 2}, \
- {"d7", 77, 2}, \
- {"d8", 79, 2}, \
- {"d9", 81, 2}, \
- {"d10", 83, 2}, \
- {"d11", 85, 2}, \
- {"d12", 87, 2}, \
- {"d13", 89, 2}, \
- {"d14", 91, 2}, \
- {"d15", 93, 2}, \
- {"q0", 63, 4}, \
- {"q1", 67, 4}, \
- {"q2", 71, 4}, \
- {"q3", 75, 4}, \
- {"q4", 79, 4}, \
- {"q5", 83, 4}, \
- {"q6", 87, 4}, \
- {"q7", 91, 4}, \
- {"q8", 95, 4}, \
- {"q9", 99, 4}, \
- {"q10", 103, 4}, \
- {"q11", 107, 4}, \
- {"q12", 111, 4}, \
- {"q13", 115, 4}, \
- {"q14", 119, 4}, \
- {"q15", 123, 4} \
+ {"d0", FIRST_VFP_REGNUM + 0, 2}, \
+ {"d1", FIRST_VFP_REGNUM + 2, 2}, \
+ {"d2", FIRST_VFP_REGNUM + 4, 2}, \
+ {"d3", FIRST_VFP_REGNUM + 6, 2}, \
+ {"d4", FIRST_VFP_REGNUM + 8, 2}, \
+ {"d5", FIRST_VFP_REGNUM + 10, 2}, \
+ {"d6", FIRST_VFP_REGNUM + 12, 2}, \
+ {"d7", FIRST_VFP_REGNUM + 14, 2}, \
+ {"d8", FIRST_VFP_REGNUM + 16, 2}, \
+ {"d9", FIRST_VFP_REGNUM + 18, 2}, \
+ {"d10", FIRST_VFP_REGNUM + 20, 2}, \
+ {"d11", FIRST_VFP_REGNUM + 22, 2}, \
+ {"d12", FIRST_VFP_REGNUM + 24, 2}, \
+ {"d13", FIRST_VFP_REGNUM + 26, 2}, \
+ {"d14", FIRST_VFP_REGNUM + 28, 2}, \
+ {"d15", FIRST_VFP_REGNUM + 30, 2}, \
+ {"q0", FIRST_VFP_REGNUM + 0, 4}, \
+ {"q1", FIRST_VFP_REGNUM + 4, 4}, \
+ {"q2", FIRST_VFP_REGNUM + 8, 4}, \
+ {"q3", FIRST_VFP_REGNUM + 12, 4}, \
+ {"q4", FIRST_VFP_REGNUM + 16, 4}, \
+ {"q5", FIRST_VFP_REGNUM + 20, 4}, \
+ {"q6", FIRST_VFP_REGNUM + 24, 4}, \
+ {"q7", FIRST_VFP_REGNUM + 28, 4}, \
+ {"q8", FIRST_VFP_REGNUM + 32, 4}, \
+ {"q9", FIRST_VFP_REGNUM + 36, 4}, \
+ {"q10", FIRST_VFP_REGNUM + 40, 4}, \
+ {"q11", FIRST_VFP_REGNUM + 44, 4}, \
+ {"q12", FIRST_VFP_REGNUM + 48, 4}, \
+ {"q13", FIRST_VFP_REGNUM + 52, 4}, \
+ {"q14", FIRST_VFP_REGNUM + 56, 4}, \
+ {"q15", FIRST_VFP_REGNUM + 60, 4} \
}
#endif
@@ -55,6 +55,5 @@ ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A)
ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R)
ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M)
ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM)
-ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4)
ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)
ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
@@ -89,7 +89,7 @@ ARM_CORE("arm920", arm920, 4T, FL_LDSCHED, fastm
ARM_CORE("arm920t", arm920t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm922t", arm922t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm940t", arm940t, 4T, FL_LDSCHED, fastmul)
-ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS, fastmul)
+ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED, fastmul)
/* V5T Architecture Processors */
ARM_CORE("arm10tdmi", arm10tdmi, 5T, FL_LDSCHED, fastmul)
@@ -66,7 +66,6 @@ extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int);
extern bool ldm_stm_operation_p (rtx, bool, enum machine_mode mode,
bool, bool);
extern int arm_const_double_rtx (rtx);
-extern int neg_const_double_rtx_ok_for_fpa (rtx);
extern int vfp3_const_double_rtx (rtx);
extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
@@ -94,7 +93,6 @@ extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
bool);
extern bool arm_tls_referenced_p (rtx);
-extern int cirrus_memory_offset (rtx);
extern int arm_coproc_mem_operand (rtx, bool);
extern int neon_vector_mem_operand (rtx, int);
extern int neon_struct_mem_operand (rtx);
@@ -133,11 +131,7 @@ extern void arm_emit_call_insn (rtx, rtx);
extern const char *output_call (rtx *);
extern const char *output_call_mem (rtx *);
void arm_emit_movpair (rtx, rtx);
-extern const char *output_mov_long_double_fpa_from_arm (rtx *);
-extern const char *output_mov_long_double_arm_from_fpa (rtx *);
extern const char *output_mov_long_double_arm_from_arm (rtx *);
-extern const char *output_mov_double_fpa_from_arm (rtx *);
-extern const char *output_mov_double_arm_from_fpa (rtx *);
extern const char *output_move_double (rtx *, bool, int *count);
extern const char *output_move_quad (rtx *);
extern int arm_count_output_move_double_insns (rtx *);
@@ -178,8 +172,6 @@ extern int arm_apply_result_size (void);
#endif /* RTX_CODE */
-extern int arm_float_words_big_endian (void);
-
/* Thumb functions. */
extern void arm_init_expanders (void);
extern const char *thumb1_unexpanded_epilogue (void);
@@ -347,13 +347,10 @@ EnumValue
Enum(arm_arch) String(armv7e-m) Value(22)
EnumValue
-Enum(arm_arch) String(ep9312) Value(23)
+Enum(arm_arch) String(iwmmxt) Value(23)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(24)
-
-EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(25)
+Enum(arm_arch) String(iwmmxt2) Value(24)
Enum
Name(arm_fpu) Type(int)
@@ -87,7 +87,6 @@ inline static int thumb1_index_register_rtx_p (rtx, int);
static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
static int thumb_far_jump_used_p (void);
static bool thumb_force_lr_save (void);
-static rtx emit_sfm (int, int);
static unsigned arm_size_return_regs (void);
static bool arm_assemble_integer (rtx, unsigned int, int);
static void arm_print_operand (FILE *, rtx, int);
@@ -662,7 +661,7 @@ static int thumb_call_reg_needed;
#define FL_STRONG (1 << 8) /* StrongARM */
#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
#define FL_XSCALE (1 << 10) /* XScale */
-#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
+/* spare (1 << 11) */
#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
@@ -757,9 +756,6 @@ int arm_ld_sched = 0;
/* Nonzero if this chip is a StrongARM. */
int arm_tune_strongarm = 0;
-/* Nonzero if this chip is a Cirrus variant. */
-int arm_arch_cirrus = 0;
-
/* Nonzero if this chip supports Intel Wireless MMX technology. */
int arm_arch_iwmmxt = 0;
@@ -1708,7 +1704,6 @@ arm_option_override (void)
arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
- arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
@@ -1768,10 +1763,7 @@ arm_option_override (void)
#ifdef FPUTYPE_DEFAULT
target_fpu_name = FPUTYPE_DEFAULT;
#else
- if (arm_arch_cirrus)
- target_fpu_name = "maverick";
- else
- target_fpu_name = "fpe2";
+ target_fpu_name = "vfp";
#endif
ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
@@ -1783,19 +1775,6 @@ arm_option_override (void)
switch (arm_fpu_desc->model)
{
- case ARM_FP_MODEL_FPA:
- if (arm_fpu_desc->rev == 2)
- arm_fpu_attr = FPU_FPE2;
- else if (arm_fpu_desc->rev == 3)
- arm_fpu_attr = FPU_FPE3;
- else
- arm_fpu_attr = FPU_FPA;
- break;
-
- case ARM_FP_MODEL_MAVERICK:
- arm_fpu_attr = FPU_MAVERICK;
- break;
-
case ARM_FP_MODEL_VFP:
arm_fpu_attr = FPU_VFP;
break;
@@ -1804,10 +1783,6 @@ arm_option_override (void)
gcc_unreachable();
}
- if (TARGET_AAPCS_BASED
- && (arm_fpu_desc->model == ARM_FP_MODEL_FPA))
- error ("FPA is unsupported in the AAPCS");
-
if (TARGET_AAPCS_BASED)
{
if (TARGET_CALLER_INTERWORKING)
@@ -1817,11 +1792,6 @@ arm_option_override (void)
error ("AAPCS does not support -mcallee-super-interworking");
}
- /* FPA and iWMMXt are incompatible because the insn encodings overlap.
- VFP and iWMMXt however can coexist. */
- if (TARGET_IWMMXT && TARGET_HARD_FLOAT && !TARGET_VFP)
- error ("iWMMXt and non-VFP floating point unit are incompatible");
-
/* iWMMXt and NEON are incompatible. */
if (TARGET_IWMMXT && TARGET_NEON)
error ("iWMMXt and NEON are incompatible");
@@ -1860,11 +1830,9 @@ arm_option_override (void)
arm_pcs_default = ARM_PCS_ATPCS;
}
- /* For arm2/3 there is no need to do any scheduling if there is only
- a floating point emulator, or we are doing software floating-point. */
- if ((TARGET_SOFT_FLOAT
- || (TARGET_FPA && arm_fpu_desc->rev))
- && (tune_flags & FL_MODE32) == 0)
+ /* For arm2/3 there is no need to do any scheduling if we are doing
+ software floating-point. */
+ if (TARGET_SOFT_FLOAT && (tune_flags & FL_MODE32) == 0)
flag_schedule_insns = flag_schedule_insns_after_reload = 0;
/* Use the cp15 method if it is available. */
@@ -2356,14 +2324,8 @@ use_return_insn (int iscond, rtx sibling)
if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
return 0;
- /* Can't be done if any of the FPA regs are pushed,
+ /* Can't be done if any of the VFP regs are pushed,
since this also requires an insn. */
- if (TARGET_HARD_FLOAT && TARGET_FPA)
- for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
- if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
- return 0;
-
- /* Likewise VFP regs. */
if (TARGET_HARD_FLOAT && TARGET_VFP)
for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
@@ -3466,11 +3428,6 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
{
rtx tem;
- /* To keep things simple, always use the Cirrus cfcmp64 if it is
- available. */
- if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
- return code;
-
if (code == GT || code == LE
|| (!TARGET_ARM && (code == GTU || code == LEU)))
{
@@ -3720,16 +3677,6 @@ arm_libcall_value_1 (enum machine_mode mode)
{
if (TARGET_AAPCS_BASED)
return aapcs_libcall_value (mode);
- else if (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_FPA
- && GET_MODE_CLASS (mode) == MODE_FLOAT)
- return gen_rtx_REG (mode, FIRST_FPA_REGNUM);
- else if (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_MAVERICK
- && GET_MODE_CLASS (mode) == MODE_FLOAT)
- return gen_rtx_REG (mode, FIRST_CIRRUS_FP_REGNUM);
else if (TARGET_IWMMXT_ABI
&& arm_vector_mode_supported_p (mode))
return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM);
@@ -3767,16 +3714,8 @@ arm_function_value_regno_p (const unsigned int regno)
&& TARGET_VFP
&& TARGET_HARD_FLOAT
&& regno == FIRST_VFP_REGNUM)
- || (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_MAVERICK
- && regno == FIRST_CIRRUS_FP_REGNUM)
|| (TARGET_IWMMXT_ABI
- && regno == FIRST_IWMMXT_REGNUM)
- || (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_FPA
- && regno == FIRST_FPA_REGNUM))
+ && regno == FIRST_IWMMXT_REGNUM))
return true;
return false;
@@ -3791,15 +3730,8 @@ arm_apply_result_size (void)
if (TARGET_32BIT)
{
- if (TARGET_HARD_FLOAT_ABI)
- {
- if (TARGET_VFP)
- size += 32;
- if (TARGET_FPA)
- size += 12;
- if (TARGET_MAVERICK)
- size += 8;
- }
+ if (TARGET_HARD_FLOAT_ABI && TARGET_VFP)
+ size += 32;
if (TARGET_IWMMXT_ABI)
size += 8;
}
@@ -3950,28 +3882,6 @@ arm_return_in_memory (const_tree type, const_tree fntype)
return true;
}
-/* Indicate whether or not words of a double are in big-endian order. */
-
-int
-arm_float_words_big_endian (void)
-{
- if (TARGET_MAVERICK)
- return 0;
-
- /* For FPA, float words are always big-endian. For VFP, floats words
- follow the memory system mode. */
-
- if (TARGET_FPA)
- {
- return 1;
- }
-
- if (TARGET_VFP)
- return (TARGET_BIG_END ? 1 : 0);
-
- return 1;
-}
-
const struct pcs_attribute_arg
{
const char *arg;
@@ -5851,9 +5761,8 @@ arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
- && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
- && (mode == SFmode || mode == DFmode
- || (TARGET_MAVERICK && mode == DImode)))
+ && TARGET_VFP
+ && (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
&& INTVAL (index) > -1024
&& (INTVAL (index) & 3) == 0);
@@ -5972,9 +5881,8 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
/* ??? Combine arm and thumb2 coprocessor addressing modes. */
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
- && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
- && (mode == SFmode || mode == DFmode
- || (TARGET_MAVERICK && mode == DImode)))
+ && TARGET_VFP
+ && (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
/* Thumb-2 allows only > -256 index range for it's core register
load/stores. Since we allow SF/DF in core registers, we have
@@ -6687,9 +6595,8 @@ arm_legitimize_reload_address (rtx *p,
/* Detect coprocessor load/stores. */
bool coproc_p = ((TARGET_HARD_FLOAT
- && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
- && (mode == SFmode || mode == DFmode
- || (mode == DImode && TARGET_MAVERICK)))
+ && TARGET_VFP
+ && (mode == SFmode || mode == DFmode))
|| (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode))
|| (TARGET_NEON
@@ -8545,7 +8452,6 @@ fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
/* Implement TARGET_REGISTER_MOVE_COST.
- Moves between FPA_REGS and GENERAL_REGS are two memory insns.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
it is typically more expensive than a single memory access. We set
the cost to less than two memory accesses so that floating
@@ -8557,20 +8463,14 @@ arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
{
if (TARGET_32BIT)
{
- if ((from == FPA_REGS && to != FPA_REGS)
- || (from != FPA_REGS && to == FPA_REGS))
- return 20;
- else if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
- || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
+ if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
+ || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
return 15;
else if ((from == IWMMXT_REGS && to != IWMMXT_REGS)
|| (from != IWMMXT_REGS && to == IWMMXT_REGS))
return 4;
else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS)
return 20;
- else if ((from == CIRRUS_REGS && to != CIRRUS_REGS)
- || (from != CIRRUS_REGS && to == CIRRUS_REGS))
- return 20;
else
return 2;
}
@@ -8628,7 +8528,7 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
return cost;
}
- /* XXX This is not strictly true for the FPA. */
+ /* XXX Is this strictly true? */
if (REG_NOTE_KIND (link) == REG_DEP_ANTI
|| REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
return 0;
@@ -9477,43 +9377,6 @@ neon_element_bits (enum machine_mode mode)
/* Predicates for `match_operand' and `match_operator'. */
-/* Return nonzero if OP is a valid Cirrus memory address pattern. */
-int
-cirrus_memory_offset (rtx op)
-{
- /* Reject eliminable registers. */
- if (! (reload_in_progress || reload_completed)
- && ( reg_mentioned_p (frame_pointer_rtx, op)
- || reg_mentioned_p (arg_pointer_rtx, op)
- || reg_mentioned_p (virtual_incoming_args_rtx, op)
- || reg_mentioned_p (virtual_outgoing_args_rtx, op)
- || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
- || reg_mentioned_p (virtual_stack_vars_rtx, op)))
- return 0;
-
- if (GET_CODE (op) == MEM)
- {
- rtx ind;
-
- ind = XEXP (op, 0);
-
- /* Match: (mem (reg)). */
- if (GET_CODE (ind) == REG)
- return 1;
-
- /* Match:
- (mem (plus (reg)
- (const))). */
- if (GET_CODE (ind) == PLUS
- && GET_CODE (XEXP (ind, 0)) == REG
- && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
- && GET_CODE (XEXP (ind, 1)) == CONST_INT)
- return 1;
- }
-
- return 0;
-}
-
/* Return TRUE if OP is a valid coprocessor memory address pattern.
WB is true if full writeback address modes are allowed and is false
if limited writeback address modes (POST_INC and PRE_DEC) are
@@ -11613,8 +11476,6 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
case LE:
case GT:
case GE:
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
- return CCFPmode;
return CCFPEmode;
default:
@@ -11719,11 +11580,6 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
if (GET_MODE (x) == DImode || GET_MODE (y) == DImode)
{
- /* To keep things simple, always use the Cirrus cfcmp64 if it is
- available. */
- if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
- return CCmode;
-
switch (op)
{
case EQ:
@@ -11791,7 +11647,6 @@ arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y, rtx scratch)
cc_reg = gen_rtx_REG (mode, CC_REGNUM);
if (dimode_comparison
- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
&& mode != CC_CZmode)
{
rtx clobber, set;
@@ -13934,47 +13789,6 @@ output_call_mem (rtx *operands)
}
-/* Output a move from arm registers to an fpa registers.
- OPERANDS[0] is an fpa register.
- OPERANDS[1] is the first registers of an arm register pair. */
-const char *
-output_mov_long_double_fpa_from_arm (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[1]);
- rtx ops[3];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
-
- output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
- output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
-
- return "";
-}
-
-/* Output a move from an fpa register to arm registers.
- OPERANDS[0] is the first registers of an arm register pair.
- OPERANDS[1] is an fpa register. */
-const char *
-output_mov_long_double_arm_from_fpa (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[0]);
- rtx ops[3];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
-
- output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
- output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
- return "";
-}
-
/* Output a move from arm registers to arm registers of a long double
OPERANDS[0] is the destination.
OPERANDS[1] is the source. */
@@ -14027,42 +13841,6 @@ arm_emit_movpair (rtx dest, rtx src)
emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src));
}
-/* Output a move from arm registers to an fpa registers.
- OPERANDS[0] is an fpa register.
- OPERANDS[1] is the first registers of an arm register pair. */
-const char *
-output_mov_double_fpa_from_arm (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[1]);
- rtx ops[2];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
- output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
- return "";
-}
-
-/* Output a move from an fpa register to arm registers.
- OPERANDS[0] is the first registers of an arm register pair.
- OPERANDS[1] is an fpa register. */
-const char *
-output_mov_double_arm_from_fpa (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[0]);
- rtx ops[2];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
- output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
- return "";
-}
-
/* Output a move between double words. It must be REG<-MEM
or MEM<-REG. */
const char *
@@ -16105,68 +15883,7 @@ arm_size_return_regs (void)
return GET_MODE_SIZE (mode);
}
-static rtx
-emit_sfm (int base_reg, int count)
-{
- rtx par;
- rtx dwarf;
- rtx tmp, reg;
- int i;
-
- par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
-
- reg = gen_rtx_REG (XFmode, base_reg++);
-
- XVECEXP (par, 0, 0)
- = gen_rtx_SET (VOIDmode,
- gen_frame_mem
- (BLKmode,
- gen_rtx_PRE_MODIFY (Pmode,
- stack_pointer_rtx,
- plus_constant
- (Pmode, stack_pointer_rtx,
- -12 * count))
- ),
- gen_rtx_UNSPEC (BLKmode,
- gen_rtvec (1, reg),
- UNSPEC_PUSH_MULT));
- tmp = gen_rtx_SET (VOIDmode,
- gen_frame_mem (XFmode, stack_pointer_rtx), reg);
- RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, 1) = tmp;
-
- for (i = 1; i < count; i++)
- {
- reg = gen_rtx_REG (XFmode, base_reg++);
- XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
-
- tmp = gen_rtx_SET (VOIDmode,
- gen_frame_mem (XFmode,
- plus_constant (Pmode,
- stack_pointer_rtx,
- i * 12)),
- reg);
- RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, i + 1) = tmp;
- }
-
- tmp = gen_rtx_SET (VOIDmode,
- stack_pointer_rtx,
- plus_constant (Pmode, stack_pointer_rtx, -12 * count));
-
- RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, 0) = tmp;
-
- par = emit_insn (par);
- add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
-
- return par;
-}
-
-
/* Return true if the current function needs to save/restore LR. */
-
static bool
thumb_force_lr_save (void)
{
@@ -16179,7 +15896,6 @@ thumb_force_lr_save (void)
/* Return true if r3 is used by any of the tail call insns in the
current function. */
-
static bool
any_sibcall_uses_r3 (void)
{
@@ -16317,17 +16033,10 @@ arm_get_frame_offsets (void)
}
func_type = arm_current_func_type ();
- if (! IS_VOLATILE (func_type))
- {
- /* Space for saved FPA registers. */
- for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
- if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
- saved += 12;
-
- /* Space for saved VFP registers. */
- if (TARGET_HARD_FLOAT && TARGET_VFP)
- saved += arm_get_vfp_saved_size ();
- }
+ /* Space for saved VFP registers. */
+ if (! IS_VOLATILE (func_type)
+ && TARGET_HARD_FLOAT && TARGET_VFP)
+ saved += arm_get_vfp_saved_size ();
}
else /* TARGET_THUMB1 */
{
@@ -16523,55 +16232,6 @@ arm_save_coproc_regs(void)
saved_size += 8;
}
- /* Save any floating point call-saved registers used by this
- function. */
- if (TARGET_FPA_EMU2)
- {
- for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
- if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
- {
- insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
- insn = gen_rtx_MEM (XFmode, insn);
- insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += 12;
- }
- }
- else
- {
- start_reg = LAST_FPA_REGNUM;
-
- for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
- {
- if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
- {
- if (start_reg - reg == 3)
- {
- insn = emit_sfm (reg, 4);
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += 48;
- start_reg = reg - 1;
- }
- }
- else
- {
- if (start_reg != reg)
- {
- insn = emit_sfm (reg + 1, start_reg - reg);
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += (start_reg - reg) * 12;
- }
- start_reg = reg - 1;
- }
- }
-
- if (start_reg != reg)
- {
- insn = emit_sfm (reg + 1, start_reg - reg);
- saved_size += (start_reg - reg) * 12;
- RTX_FRAME_RELATED_P (insn) = 1;
- }
- }
if (TARGET_HARD_FLOAT && TARGET_VFP)
{
start_reg = FIRST_VFP_REGNUM;
@@ -17128,16 +16788,6 @@ arm_print_operand (FILE *stream, rtx x, int code)
fprintf (stream, "%s", arithmetic_instr (x, 1));
return;
- /* Truncate Cirrus shift counts. */
- case 's':
- if (GET_CODE (x) == CONST_INT)
- {
- fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
- return;
- }
- arm_print_operand (stream, x, 0);
- return;
-
case 'I':
fprintf (stream, "%s", arithmetic_instr (x, 0));
return;
@@ -17324,44 +16974,15 @@ arm_print_operand (FILE *stream, rtx x, int code)
stream);
return;
- /* Cirrus registers can be accessed in a variety of ways:
- single floating point (f)
- double floating point (d)
- 32bit integer (fx)
- 64bit integer (dx). */
- case 'W': /* Cirrus register in F mode. */
- case 'X': /* Cirrus register in D mode. */
- case 'Y': /* Cirrus register in FX mode. */
- case 'Z': /* Cirrus register in DX mode. */
- gcc_assert (GET_CODE (x) == REG
- && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
-
- fprintf (stream, "mv%s%s",
- code == 'W' ? "f"
- : code == 'X' ? "d"
- : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
-
- return;
-
- /* Print cirrus register in the mode specified by the register's mode. */
+ case 's':
case 'V':
- {
- int mode = GET_MODE (x);
-
- if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
- {
- output_operand_lossage ("invalid operand for code '%c'", code);
- return;
- }
-
- fprintf (stream, "mv%s%s",
- mode == DFmode ? "d"
- : mode == SImode ? "fx"
- : mode == DImode ? "dx"
- : "f", reg_names[REGNO (x)] + 2);
-
- return;
- }
+ case 'W':
+ case 'X':
+ case 'Y':
+ case 'Z':
+ /* Former Maverick support, removed after GCC-4.7. */
+ output_operand_lossage ("obsolete Maverick format code '%c'", code);
+ return;
case 'U':
if (GET_CODE (x) != REG
@@ -18046,9 +17667,7 @@ maybe_get_arm_condition_code (rtx comparison)
case CCFPEmode:
case CCFPmode:
- /* These encodings assume that AC=1 in the FPA system control
- byte. This allows us to handle all cases except UNEQ and
- LTGT. */
+ /* We can handle all cases except UNEQ and LTGT. */
switch (comp_code)
{
case GE: return ARM_GE;
@@ -18548,15 +18167,6 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
start of an even numbered register pair. */
return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK
- && IS_CIRRUS_REGNUM (regno))
- /* We have outlawed SI values in Cirrus registers because they
- reside in the lower 32 bits, but SF values reside in the
- upper 32 bits. This causes gcc all sorts of grief. We can't
- even split the registers into pairs because Cirrus SI values
- get sign extended to 64bits-- aldyh. */
- return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
-
if (TARGET_HARD_FLOAT && TARGET_VFP
&& IS_VFP_REGNUM (regno))
{
@@ -18606,12 +18216,7 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
/* We only allow integers in the fake hard registers. */
return GET_MODE_CLASS (mode) == MODE_INT;
- /* The only registers left are the FPA registers
- which we only allow to hold FP values. */
- return (TARGET_HARD_FLOAT && TARGET_FPA
- && GET_MODE_CLASS (mode) == MODE_FLOAT
- && regno >= FIRST_FPA_REGNUM
- && regno <= LAST_FPA_REGNUM);
+ return FALSE;
}
/* Implement MODES_TIEABLE_P. */
@@ -18665,9 +18270,6 @@ arm_regno_class (int regno)
if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
return TARGET_THUMB2 ? CC_REG : NO_REGS;
- if (IS_CIRRUS_REGNUM (regno))
- return CIRRUS_REGS;
-
if (IS_VFP_REGNUM (regno))
{
if (regno <= D7_VFP_REGNUM)
@@ -18684,7 +18286,7 @@ arm_regno_class (int regno)
if (IS_IWMMXT_GR_REGNUM (regno))
return IWMMXT_GR_REGS;
- return FPA_REGS;
+ return NO_REGS;
}
/* Handle a special case when computing the offset
@@ -23600,10 +23202,7 @@ arm_file_start (void)
if (TARGET_SOFT_FLOAT)
{
- if (TARGET_VFP)
- fpu_name = "softvfp";
- else
- fpu_name = "softfpa";
+ fpu_name = "softvfp";
}
else
{
@@ -24502,11 +24101,6 @@ arm_dbx_register_number (unsigned int regno)
if (regno < 16)
return regno;
- /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
- compatibility. The EABI defines them as registers 96-103. */
- if (IS_FPA_REGNUM (regno))
- return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
-
if (IS_VFP_REGNUM (regno))
{
/* See comment in arm_dwarf_register_span. */
@@ -24608,12 +24202,6 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
reg_size = 8;
fprintf (asm_out_file, "\t.vsave {");
}
- else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
- {
- /* FPA registers are done differently. */
- asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
- return;
- }
else
/* Unknown register type. */
abort ();
@@ -25310,7 +24898,7 @@ arm_mangle_type (const_tree type)
static const int thumb_core_reg_alloc_order[] =
{
3, 2, 1, 0, 4, 5, 6, 7,
- 14, 12, 8, 9, 10, 11, 13, 15
+ 14, 12, 8, 9, 10, 11
};
/* Adjust register allocation order when compiling for Thumb. */
@@ -25393,13 +24981,6 @@ arm_conditional_register_usage (void)
{
int regno;
- if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA)
- {
- for (regno = FIRST_FPA_REGNUM;
- regno <= LAST_FPA_REGNUM; ++regno)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- }
-
if (TARGET_THUMB1 && optimize_size)
{
/* When optimizing for size on Thumb-1, it's better not
@@ -25416,32 +24997,17 @@ arm_conditional_register_usage (void)
if (TARGET_THUMB1)
fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
- if (TARGET_32BIT && TARGET_HARD_FLOAT)
+ if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP)
{
- if (TARGET_MAVERICK)
- {
- for (regno = FIRST_FPA_REGNUM;
- regno <= LAST_FPA_REGNUM; ++ regno)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- for (regno = FIRST_CIRRUS_FP_REGNUM;
- regno <= LAST_CIRRUS_FP_REGNUM; ++ regno)
- {
- fixed_regs[regno] = 0;
- call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4;
- }
- }
- if (TARGET_VFP)
+ /* VFPv3 registers are disabled when earlier VFP
+ versions are selected due to the definition of
+ LAST_VFP_REGNUM. */
+ for (regno = FIRST_VFP_REGNUM;
+ regno <= LAST_VFP_REGNUM; ++ regno)
{
- /* VFPv3 registers are disabled when earlier VFP
- versions are selected due to the definition of
- LAST_VFP_REGNUM. */
- for (regno = FIRST_VFP_REGNUM;
- regno <= LAST_VFP_REGNUM; ++ regno)
- {
- fixed_regs[regno] = 0;
- call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16
- || regno >= FIRST_VFP_REGNUM + 32;
- }
+ fixed_regs[regno] = 0;
+ call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16
+ || regno >= FIRST_VFP_REGNUM + 32;
}
}
@@ -91,8 +91,6 @@ extern char arm_arch_name[];
builtin_assert ("machine=arm"); \
\
builtin_define (arm_arch_name); \
- if (arm_arch_cirrus) \
- builtin_define ("__MAVERICK__"); \
if (arm_arch_xscale) \
builtin_define ("__XSCALE__"); \
if (arm_arch_iwmmxt) \
@@ -192,8 +190,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
/* Use hardware floating point calling convention. */
#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
-#define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
-#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
#define TARGET_IWMMXT (arm_arch_iwmmxt)
#define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
@@ -221,8 +217,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
/* Thumb-1 only. */
#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
-/* FPA emulator without LFM. */
-#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
/* The following two macros concern the ability to execute coprocessor
instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
@@ -326,10 +320,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
enum arm_fp_model
{
ARM_FP_MODEL_UNKNOWN,
- /* FPA model (Hardware or software). */
- ARM_FP_MODEL_FPA,
- /* Cirrus Maverick floating point model. */
- ARM_FP_MODEL_MAVERICK,
/* VFP floating point model. */
ARM_FP_MODEL_VFP
};
@@ -408,9 +398,6 @@ extern int thumb1_code;
/* Nonzero if this chip is a StrongARM. */
extern int arm_tune_strongarm;
-/* Nonzero if this chip is a Cirrus variant. */
-extern int arm_arch_cirrus;
-
/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
extern int arm_arch_iwmmxt;
@@ -511,11 +498,6 @@ extern int arm_arch_thumb_hwdiv;
This is always false, even when in big-endian mode. */
#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
-/* Define this if most significant word of doubles is the lowest numbered.
- The rules are different based on whether or not we use FPA-format,
- VFP-format or some other floating point co-processor's format doubles. */
-#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
-
#define UNITS_PER_WORD 4
/* True if natural alignment is used for doubleword types. */
@@ -634,7 +616,7 @@ extern int arm_arch_thumb_hwdiv;
/* Standard register usage. */
-/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
+/* Register allocation in ARM Procedure Call Standard
(S - saved over call).
r0 * argument word/integer result
@@ -650,11 +632,6 @@ extern int arm_arch_thumb_hwdiv;
r14 (lr) link address/workspace
r15 F (pc) program counter
- f0 floating point result
- f1-f3 floating point scratch
-
- f4-f7 S floating point variable
-
cc This is NOT a real register, but is used internally
to represent things that use or set the condition
codes.
@@ -668,11 +645,6 @@ extern int arm_arch_thumb_hwdiv;
*: See TARGET_CONDITIONAL_REGISTER_USAGE */
-/*
- mvf0 Cirrus floating point result
- mvf1-mvf3 Cirrus floating point scratch
- mvf4-mvf15 S Cirrus floating point variable. */
-
/* s0-s15 VFP scratch (aka d0-d7).
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
@@ -694,34 +666,30 @@ extern int arm_arch_thumb_hwdiv;
[| saved r2 value |]
[| saved r1 value |]
[| saved r0 value |]
- [| saved f7 value |] three words
- [| saved f6 value |] three words
- [| saved f5 value |] three words
- [| saved f4 value |] three words
r0-r3 are not normally saved in a C function. */
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
-#define FIXED_REGISTERS \
-{ \
- 0,0,0,0,0,0,0,0, \
- 0,0,0,0,0,1,0,1, \
- 0,0,0,0,0,0,0,0, \
- 1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1 \
+#define FIXED_REGISTERS \
+{ \
+ /* Core regs. */ \
+ 0,0,0,0,0,0,0,0, \
+ 0,0,0,0,0,1,0,1, \
+ /* VFP regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ /* IWMMXT regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1, \
+ /* Specials. */ \
+ 1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -732,26 +700,26 @@ extern int arm_arch_thumb_hwdiv;
Aside from that, you can include as many other registers as you like.
The CC is not preserved over function calls on the ARM 6, so it is
easier to assume this for all. SFP is preserved, since FP is. */
-#define CALL_USED_REGISTERS \
-{ \
- 1,1,1,1,0,0,0,0, \
- 0,0,0,0,1,1,1,1, \
- 1,1,1,1,0,0,0,0, \
- 1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1 \
+#define CALL_USED_REGISTERS \
+{ \
+ /* Core regs. */ \
+ 1,1,1,1,0,0,0,0, \
+ 0,0,0,0,1,1,1,1, \
+ /* VFP Regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ /* IWMMXT regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1, \
+ /* Specials. */ \
+ 1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -868,34 +836,24 @@ extern int arm_arch_thumb_hwdiv;
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM SP_REGNUM
-/* ARM floating pointer registers. */
-#define FIRST_FPA_REGNUM 16
-#define LAST_FPA_REGNUM 23
-#define IS_FPA_REGNUM(REGNUM) \
- (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
+#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
+#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
+#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
+#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
-#define FIRST_IWMMXT_GR_REGNUM 43
-#define LAST_IWMMXT_GR_REGNUM 46
-#define FIRST_IWMMXT_REGNUM 47
-#define LAST_IWMMXT_REGNUM 62
#define IS_IWMMXT_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
#define IS_IWMMXT_GR_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 25
+#define FRAME_POINTER_REGNUM 102
/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 26
+#define ARG_POINTER_REGNUM 103
-#define FIRST_CIRRUS_FP_REGNUM 27
-#define LAST_CIRRUS_FP_REGNUM 42
-#define IS_CIRRUS_REGNUM(REGNUM) \
- (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
-
-#define FIRST_VFP_REGNUM 63
-#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
+#define FIRST_VFP_REGNUM 16
+#define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
#define LAST_VFP_REGNUM \
(TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
@@ -908,9 +866,9 @@ extern int arm_arch_thumb_hwdiv;
in various parts of the backend, we implement as "fake" single-precision
registers (which would be S32-S63, but cannot be used in that way). The
following macros define these ranges of registers. */
-#define LAST_LO_VFP_REGNUM 94
-#define FIRST_HI_VFP_REGNUM 95
-#define LAST_HI_VFP_REGNUM 126
+#define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
+#define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
+#define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
((REGNUM) <= LAST_LO_VFP_REGNUM)
@@ -931,11 +889,10 @@ extern int arm_arch_thumb_hwdiv;
((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
-/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
-/* + 16 Cirrus registers take us up to 43. */
+/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
-/* VFP (VFP3) adds 32 (64) + 1 more. */
-#define FIRST_PSEUDO_REGISTER 128
+/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
+#define FIRST_PSEUDO_REGISTER 104
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -955,11 +912,10 @@ extern int arm_arch_thumb_hwdiv;
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
- On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
- mode. */
+ On the ARM core regs are UNITS_PER_WORD bits wide. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_32BIT \
- && REGNO >= FIRST_FPA_REGNUM \
+ && REGNO > PC_REGNUM \
&& REGNO != FRAME_POINTER_REGNUM \
&& REGNO != ARG_POINTER_REGNUM) \
&& !IS_VFP_REGNUM (REGNO) \
@@ -1003,26 +959,44 @@ extern int arm_regs_in_sequence[];
pressure when both single- and double-precision registers are used in a
function. */
+#define VREG(X) (FIRST_VFP_REGNUM + (X))
+#define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
+#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
+
#define REG_ALLOC_ORDER \
{ \
- 3, 2, 1, 0, 12, 14, 4, 5, \
- 6, 7, 8, 10, 9, 11, 13, 15, \
- 16, 17, 18, 19, 20, 21, 22, 23, \
- 27, 28, 29, 30, 31, 32, 33, 34, \
- 35, 36, 37, 38, 39, 40, 41, 42, \
- 43, 44, 45, 46, 47, 48, 49, 50, \
- 51, 52, 53, 54, 55, 56, 57, 58, \
- 59, 60, 61, 62, \
- 24, 25, 26, \
- 95, 96, 97, 98, 99, 100, 101, 102, \
- 103, 104, 105, 106, 107, 108, 109, 110, \
- 111, 112, 113, 114, 115, 116, 117, 118, \
- 119, 120, 121, 122, 123, 124, 125, 126, \
- 78, 77, 76, 75, 74, 73, 72, 71, \
- 70, 69, 68, 67, 66, 65, 64, 63, \
- 79, 80, 81, 82, 83, 84, 85, 86, \
- 87, 88, 89, 90, 91, 92, 93, 94, \
- 127 \
+ /* General registers. */ \
+ 3, 2, 1, 0, 12, 14, 4, 5, \
+ 6, 7, 8, 9, 10, 11, \
+ /* High VFP registers. */ \
+ VREG(32), VREG(33), VREG(34), VREG(35), \
+ VREG(36), VREG(37), VREG(38), VREG(39), \
+ VREG(40), VREG(41), VREG(42), VREG(43), \
+ VREG(44), VREG(45), VREG(46), VREG(47), \
+ VREG(48), VREG(49), VREG(50), VREG(51), \
+ VREG(52), VREG(53), VREG(54), VREG(55), \
+ VREG(56), VREG(57), VREG(58), VREG(59), \
+ VREG(60), VREG(61), VREG(62), VREG(63), \
+ /* VFP argument registers. */ \
+ VREG(15), VREG(14), VREG(13), VREG(12), \
+ VREG(11), VREG(10), VREG(9), VREG(8), \
+ VREG(7), VREG(6), VREG(5), VREG(4), \
+ VREG(3), VREG(2), VREG(1), VREG(0), \
+ /* VFP call-saved registers. */ \
+ VREG(16), VREG(17), VREG(18), VREG(19), \
+ VREG(20), VREG(21), VREG(22), VREG(23), \
+ VREG(24), VREG(25), VREG(26), VREG(27), \
+ VREG(28), VREG(29), VREG(30), VREG(31), \
+ /* IWMMX registers. */ \
+ WREG(0), WREG(1), WREG(2), WREG(3), \
+ WREG(4), WREG(5), WREG(6), WREG(7), \
+ WREG(8), WREG(9), WREG(10), WREG(11), \
+ WREG(12), WREG(13), WREG(14), WREG(15), \
+ WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
+ /* Registers not for general use. */ \
+ CC_REGNUM, VFPCC_REGNUM, \
+ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
+ SP_REGNUM, PC_REGNUM \
}
/* Use different register alloc ordering for Thumb. */
@@ -1041,27 +1015,26 @@ extern int arm_regs_in_sequence[];
/* Register and constant classes. */
-/* Register classes: used to be simple, just all ARM regs or all FPA regs
- Now that the Thumb is involved it has become more complicated. */
+/* Register classes. */
enum reg_class
{
NO_REGS,
- FPA_REGS,
- CIRRUS_REGS,
+ LO_REGS,
+ STACK_REG,
+ BASE_REGS,
+ HI_REGS,
+ GENERAL_REGS,
+ CORE_REGS,
VFP_D0_D7_REGS,
VFP_LO_REGS,
VFP_HI_REGS,
VFP_REGS,
- IWMMXT_GR_REGS,
IWMMXT_REGS,
- LO_REGS,
- STACK_REG,
- BASE_REGS,
- HI_REGS,
+ IWMMXT_GR_REGS,
CC_REG,
VFPCC_REG,
- GENERAL_REGS,
- CORE_REGS,
+ SFP_REG,
+ AFP_REG,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1072,22 +1045,20 @@ enum reg_class
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
- "FPA_REGS", \
- "CIRRUS_REGS", \
+ "LO_REGS", \
+ "STACK_REG", \
+ "BASE_REGS", \
+ "HI_REGS", \
+ "GENERAL_REGS", \
+ "CORE_REGS", \
"VFP_D0_D7_REGS", \
"VFP_LO_REGS", \
"VFP_HI_REGS", \
"VFP_REGS", \
- "IWMMXT_GR_REGS", \
"IWMMXT_REGS", \
- "LO_REGS", \
- "STACK_REG", \
- "BASE_REGS", \
- "HI_REGS", \
+ "IWMMXT_GR_REGS", \
"CC_REG", \
"VFPCC_REG", \
- "GENERAL_REGS", \
- "CORE_REGS", \
"ALL_REGS", \
}
@@ -1097,23 +1068,23 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
- { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
- { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
- { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
- { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
- { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
- { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
- { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
- { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
{ 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
{ 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
{ 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
- { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
- { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
- { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
- { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
- { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
+ { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
+ { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
+ { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
+ { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
+ { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
+ { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
+ { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
+ { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 } /* ALL_REGS */ \
}
/* Any of the VFP register classes. */
@@ -1127,14 +1098,11 @@ enum reg_class
or could index an array. */
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
-/* FPA registers can't do subreg as all values are reformatted to internal
- precision. In VFPv1, VFP registers could only be accessed in the mode
- they were set, so subregs would be invalid there too. However, we don't
- support VFPv1 at the moment, and the restriction was lifted in VFPv2. */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
- ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
- : 0)
+/* In VFPv1, VFP registers could only be accessed in the mode they
+ were set, so subregs would be invalid there. However, we don't
+ support VFPv1 at the moment, and the restriction was lifted in
+ VFPv2. */
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) 0
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
@@ -1196,21 +1164,16 @@ enum reg_class
? coproc_secondary_reload_class (MODE, X, FALSE) : \
(TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
coproc_secondary_reload_class (MODE, X, TRUE) : \
- /* Cannot load constants into Cirrus registers. */ \
- (TARGET_MAVERICK && TARGET_HARD_FLOAT \
- && (CLASS) == CIRRUS_REGS \
- && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
+ (TARGET_32BIT ? \
+ (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
+ && CONSTANT_P (X)) \
? GENERAL_REGS : \
- (TARGET_32BIT ? \
- (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
- && CONSTANT_P (X)) \
- ? GENERAL_REGS : \
- (((MODE) == HImode && ! arm_arch4 \
- && (GET_CODE (X) == MEM \
- || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
- && true_regnum (X) == -1))) \
- ? GENERAL_REGS : NO_REGS) \
- : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
+ (((MODE) == HImode && ! arm_arch4 \
+ && (GET_CODE (X) == MEM \
+ || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
+ && true_regnum (X) == -1))) \
+ ? GENERAL_REGS : NO_REGS) \
+ : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
@@ -1254,9 +1217,10 @@ do { \
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
- ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
+ ARM regs are UNITS_PER_WORD bits.
+ FIXME: Is this true for iWMMX? */
#define CLASS_MAX_NREGS(CLASS, MODE) \
- (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
+ (ARM_NUM_REGS (MODE))
/* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */
@@ -28,18 +28,17 @@
;;---------------------------------------------------------------------------
;; Constants
-;; Register numbers
+;; Register numbers -- All machine registers should be defined here
(define_constants
- [(R0_REGNUM 0) ; First CORE register
- (R1_REGNUM 1) ; Second CORE register
- (IP_REGNUM 12) ; Scratch register
- (SP_REGNUM 13) ; Stack pointer
- (LR_REGNUM 14) ; Return address register
- (PC_REGNUM 15) ; Program counter
- (CC_REGNUM 24) ; Condition code pseudo register
- (LAST_ARM_REGNUM 15) ;
- (FPA_F0_REGNUM 16) ; FIRST_FPA_REGNUM
- (FPA_F7_REGNUM 23) ; LAST_FPA_REGNUM
+ [(R0_REGNUM 0) ; First CORE register
+ (R1_REGNUM 1) ; Second CORE register
+ (IP_REGNUM 12) ; Scratch register
+ (SP_REGNUM 13) ; Stack pointer
+ (LR_REGNUM 14) ; Return address register
+ (PC_REGNUM 15) ; Program counter
+ (LAST_ARM_REGNUM 15) ;
+ (CC_REGNUM 100) ; Condition code pseudo register
+ (VFPCC_REGNUM 101) ; VFP Condition code pseudo register
]
)
;; 3rd operand to select_dominance_cc_mode
@@ -178,7 +177,7 @@
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
; performance we should try and group them together).
-(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
+(define_attr "fpu" "none,vfp"
(const (symbol_ref "arm_fpu_attr")))
; LENGTH of an instruction (in bytes)
@@ -92,9 +92,8 @@
} \
while (0)
-/* NWFPE always understands FPA instructions. */
#undef FPUTYPE_DEFAULT
-#define FPUTYPE_DEFAULT "fpe3"
+#define FPUTYPE_DEFAULT "vfp"
/* Call the function profiler with a given profile label. */
#undef ARM_FUNCTION_PROFILER
@@ -19,11 +19,6 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
-;; Additional register numbers
-(define_constants
- [(VFPCC_REGNUM 127)]
-)
-
;; The VFP "type" attributes differ from those used in the FPA model.
;; fcpys Single precision cpy.
;; ffariths Single precision abs, neg.