From patchwork Wed Oct 12 22:42:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 119318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 7D6C5B6F77 for ; Thu, 13 Oct 2011 09:42:40 +1100 (EST) Received: (qmail 15748 invoked by alias); 12 Oct 2011 22:42:38 -0000 Received: (qmail 15730 invoked by uid 22791); 12 Oct 2011 22:42:37 -0000 X-SWARE-Spam-Status: No, hits=-6.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 12 Oct 2011 22:42:15 +0000 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p9CMgDi9012959 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 12 Oct 2011 18:42:13 -0400 Received: from anchor.twiddle.net (vpn-237-55.phx2.redhat.com [10.3.237.55]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p9CMgCTj004048; Wed, 12 Oct 2011 18:42:12 -0400 Message-ID: <4E9617C4.9070209@redhat.com> Date: Wed, 12 Oct 2011 15:42:12 -0700 From: Richard Henderson User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:7.0) Gecko/20110927 Thunderbird/7.0 MIME-Version: 1.0 To: dje.gcc@gmail.com, uweigand@de.ibm.com CC: GCC Patches Subject: [rs6000, spu] Add vec_perm named pattern X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The generic support for vector permutation will allow for automatic lowering to V*QImode, so all we need to add to support for these targets is the single V16QI pattern that represents the base permutation insn. I'm not touching any of the other ways that the permutation insn could be generated. After the generic support is added, I'll leave it to the port maintainers to determine what they want to keep. I suspect in many cases using the generic __builtin_shuffle plus some casting in the target-specific header files would be sufficient, eliminating several dozen builtins. Ok? r~ * config/rs6000/altivec.md (vec_permv16qi): New. * config/spu/spu.md (vec_permv16qi): New. commit f2d8929afb989a09d7e287dc171607440bbbbc1a Author: Richard Henderson Date: Mon Oct 10 12:35:25 2011 -0700 rs6000: Implement vec_permv16qi. commit a67ea08189a4399d6ade00c15e69447304f85f96 Author: Richard Henderson Date: Mon Oct 10 12:35:50 2011 -0700 spu: Implement vec_permv16qi. diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index 676d54e..00cfaa4 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -4395,6 +4395,18 @@ selb\t%0,%4,%0,%3" "shufb\t%0,%1,%2,%3" [(set_attr "type" "shuf")]) +(define_expand "vec_permv16qi" + [(set (match_operand:V16QI 0 "spu_reg_operand" "") + (unspec:V16QI + [(match_operand:V16QI 1 "spu_reg_operand" "") + (match_operand:V16QI 2 "spu_reg_operand" "") + (match_operand:V16QI 3 "spu_reg_operand" "")] + UNSPEC_SHUFB))] + "" + { + operands[3] = gen_lowpart (TImode, operands[3]); + }) + (define_insn "nop" [(unspec_volatile [(const_int 0)] UNSPECV_NOP)] "" diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 9e7437e..84c5444 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1357,6 +1357,15 @@ "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) +(define_expand "vec_permv16qi" + [(set (match_operand:V16QI 0 "register_operand" "") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "") + (match_operand:V16QI 2 "register_operand" "") + (match_operand:V16QI 3 "register_operand" "")] + UNSPEC_VPERM))] + "TARGET_ALTIVEC" + "") + (define_insn "altivec_vrfip" ; ceil [(set (match_operand:V4SF 0 "register_operand" "=v") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]