From patchwork Thu Jul 7 20:02:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Schmidt X-Patchwork-Id: 103726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id AA8C0B6F74 for ; Fri, 8 Jul 2011 06:03:20 +1000 (EST) Received: (qmail 11365 invoked by alias); 7 Jul 2011 20:03:19 -0000 Received: (qmail 11357 invoked by uid 22791); 7 Jul 2011 20:03:18 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 07 Jul 2011 20:03:02 +0000 Received: (qmail 2197 invoked from network); 7 Jul 2011 20:03:01 -0000 Received: from unknown (HELO ?84.152.222.114?) (bernds@127.0.0.2) by mail.codesourcery.com with ESMTPA; 7 Jul 2011 20:03:01 -0000 Message-ID: <4E1610ED.2070108@codesourcery.com> Date: Thu, 07 Jul 2011 22:02:53 +0200 From: Bernd Schmidt User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110505 Lightning/1.0b3pre Thunderbird/3.1.10 MIME-Version: 1.0 To: GCC Patches Subject: [ARM] Fix PR49641 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This corrects an error in store_multiple_operation. We're only generating the writeback version of the instruction on Thumb-1, so that's where we must make sure the base register isn't also stored. The ARMv7 manual is unfortunately not totally clear that this does in fact produce unpredictable results; it seems to suggest that this is the case only for the T2 encoding. Older documentation makes it clear. Tested on arm-eabi{,mthumb}. Bernd * config/arm/arm.c (store_multiple_sequence): Avoid cases where the base reg is stored iff compiling for Thumb1. * gcc.target/arm/pr49641.c: New test. Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 175906) +++ gcc/config/arm/arm.c (working copy) @@ -9950,7 +9950,10 @@ store_multiple_sequence (rtx *operands, /* If it isn't an integer register, then we can't do this. */ if (unsorted_regs[i] < 0 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) - || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) + /* For Thumb1, we'll generate an instruction with update, + and the effects are unpredictable if the base reg is + stored. */ + || (TARGET_THUMB1 && unsorted_regs[i] == base_reg) || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) || unsorted_regs[i] > 14) return 0; Index: gcc/testsuite/gcc.target/arm/pr49641.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr49641.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr49641.c (revision 0) @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "stmia\[\\t \]*r3!\[^\\n]*r3" } } */ +typedef struct { + void *t1, *t2, *t3; +} z; +extern volatile int y; +static inline void foo(z *x) { + x->t1 = &x->t2; + x->t2 = ((void *)0); + x->t3 = &x->t1; +} +extern z v; +void bar (void) { + y = 0; + foo(&v); +}